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[/] [potato/] [trunk/] [benchmarks/] [start.S] - Blame information for rev 58

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Line No. Rev Author Line
1 13 skordal
// The Potato Processor Benchmark Applications
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// (c) Kristian Klomsten Skordal 2015 
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// Report bugs and issues on 
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// This file contains startup and initialization code for the Potato benchmark
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// applications.
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#include "platform.h"
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#include "potato.h"
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.section .init
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13 58 skordal
.align 6
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tvec_user: // User mode is not supported by Potato
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        j tvec_machine
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.align 6
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tvec_supervisor: // Supervisor mode is not supported by Potato
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        j tvec_machine
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.align 6
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tvec_hypervisor: // Hypervisor mode is not supported by Potato
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        j tvec_machine
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.align 6
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tvec_machine:
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        j exception_handler_wrapper
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.align 6
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.global _start
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_start:
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// Copies the .data section into the data memory section:
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.hidden copy_data
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copy_data:
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        la x1, __text_end       // Copy source address
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        la x2, __data_begin     // Copy destination address
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        la x3, __data_end       // Copy destination end address
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        beq x2, x3, 2f          // Skip if there is no data to copy
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1:
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        lw x4, (x1)
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        sw x4, (x2)
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        addi x1, x1, 4
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        addi x2, x2, 4
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        bne x2, x3, 1b          // Repeat as long as there is more data to copy
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2:
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.hidden clear_bss
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clear_bss:
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        la x1, __bss_begin
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        la x2, __bss_end
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        beq x1, x2, 2f          // Skip if there is no .bss section
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1:
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        sw x0, (x1)
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        addi x1, x1, 4
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        bne x1, x2, 1b
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2:
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.hidden call_main
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call_main:
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        la sp, __stack_top
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        jal main
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        csrw mtohost, a0
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1:
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        j 1b
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.section .text
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.global exception_handler_wrapper
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exception_handler_wrapper:
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        // Save all registers (even those that are saved by the IRQ handler
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        // function, to aid in debugging):
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        addi sp, sp, -124
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        sw x1, 0(sp)
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        sw x2, 4(sp)
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        sw x3, 8(sp)
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        sw x4, 12(sp)
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        sw x5, 16(sp)
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        sw x6, 20(sp)
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        sw x7, 24(sp)
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        sw x8, 28(sp)
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        sw x9, 32(sp)
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        sw x10, 36(sp)
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        sw x11, 40(sp)
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        sw x12, 44(sp)
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        sw x13, 48(sp)
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        sw x14, 52(sp)
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        sw x15, 56(sp)
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        sw x16, 60(sp)
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        sw x17, 64(sp)
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        sw x18, 68(sp)
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        sw x19, 72(sp)
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        sw x20, 76(sp)
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        sw x21, 80(sp)
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        sw x22, 84(sp)
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        sw x23, 88(sp)
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        sw x24, 92(sp)
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        sw x25, 96(sp)
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        sw x26, 100(sp)
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        sw x27, 104(sp)
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        sw x28, 108(sp)
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        sw x29, 112(sp)
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        sw x30, 116(sp)
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        sw x31, 120(sp)
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108 58 skordal
        csrr a0, mcause
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        csrr a1, mepc
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        mv a2, sp
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        jal exception_handler
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.hidden exception_return
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exception_return:
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        // Restore all registers:
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        lw x1, 0(sp)
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        lw x2, 4(sp)
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        lw x3, 8(sp)
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        lw x4, 12(sp)
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        lw x5, 16(sp)
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        lw x6, 20(sp)
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        lw x7, 24(sp)
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        lw x8, 28(sp)
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        lw x9, 32(sp)
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        lw x10, 36(sp)
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        lw x11, 40(sp)
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        lw x12, 44(sp)
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        lw x13, 48(sp)
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        lw x14, 52(sp)
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        lw x15, 56(sp)
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        lw x16, 60(sp)
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        lw x17, 64(sp)
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        lw x18, 68(sp)
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        lw x19, 72(sp)
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        lw x20, 76(sp)
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        lw x21, 80(sp)
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        lw x22, 84(sp)
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        lw x23, 88(sp)
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        lw x24, 92(sp)
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        lw x25, 96(sp)
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        lw x26, 100(sp)
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        lw x27, 104(sp)
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        lw x28, 108(sp)
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        lw x29, 112(sp)
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        lw x30, 116(sp)
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        lw x31, 120(sp)
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        addi sp, sp, 124
148 13 skordal
 
149 58 skordal
        eret
150 13 skordal
 

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