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[/] [potato/] [trunk/] [src/] [pp_wb_adapter.vhd] - Blame information for rev 45

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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.pp_types.all;
use work.pp_utilities.all;
 
--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.
entity pp_wb_adapter is
        port(
                clk   : in std_logic;
                reset : in std_logic;
 
                -- Processor data memory signals:
                signal dmem_address   : in  std_logic_vector(31 downto 0);
                signal dmem_data_in   : in  std_logic_vector(31 downto 0); -- Data in to the bus
                signal dmem_data_out  : out std_logic_vector(31 downto 0); -- Data out to the bus
                signal dmem_data_size : in  std_logic_vector( 1 downto 0);
                signal dmem_read_req  : in  std_logic;
                signal dmem_read_ack  : out std_logic;
                signal dmem_write_req : in  std_logic;
                signal dmem_write_ack : out std_logic;
 
                -- Wishbone interface:
                wb_inputs  : in wishbone_master_inputs;
                wb_outputs : out wishbone_master_outputs
        );
end entity pp_wb_adapter;
 
architecture behaviour of pp_wb_adapter is
 
        type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);
        signal state : states;
 
        signal dmem_r_ack : std_logic;
 
        function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
                return natural is
        begin
                case size is
                        when b"01" =>
                                case address(1 downto 0) is
                                        when b"00" =>
                                                return 0;
                                        when b"01" =>
                                                return 8;
                                        when b"10" =>
                                                return 16;
                                        when b"11" =>
                                                return 24;
                                        when others =>
                                                return 0;
                                end case;
                        when b"10" =>
                                if address(1) = '0' then
                                        return 0;
                                else
                                        return 16;
                                end if;
                        when others =>
                                return 0;
                end case;
        end function get_data_shift;
 
begin
 
        dmem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';
        dmem_read_ack <= dmem_r_ack;
 
        wishbone: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                state <= IDLE;
                                wb_outputs.cyc <= '0';
                                wb_outputs.stb <= '0';
                                dmem_r_ack <= '0';
                        else
                                case state is
                                        when IDLE =>
                                                dmem_r_ack <= '0';
 
                                                -- Prioritize requests from the data memory:
                                                if dmem_write_req = '1' then
                                                        wb_outputs.adr <= dmem_address;
                                                        wb_outputs.dat <= std_logic_vector(shift_left(unsigned(dmem_data_in),
                                                                get_data_shift(dmem_data_size, dmem_address)));
                                                        wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
                                                        wb_outputs.cyc <= '1';
                                                        wb_outputs.stb <= '1';
                                                        wb_outputs.we <= '1';
                                                        state <= WRITE_WAIT_ACK;
                                                elsif dmem_read_req = '1' then
                                                        wb_outputs.adr <= dmem_address;
                                                        wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);
                                                        wb_outputs.cyc <= '1';
                                                        wb_outputs.stb <= '1';
                                                        wb_outputs.we <= '0';
                                                        state <= READ_WAIT_ACK;
                                                end if;
                                        when READ_WAIT_ACK =>
                                                if wb_inputs.ack = '1' then
                                                        dmem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
                                                                get_data_shift(dmem_data_size, dmem_address)));
                                                        wb_outputs.cyc <= '0';
                                                        wb_outputs.stb <= '0';
                                                        dmem_r_ack <= '1';
                                                        state <= IDLE;
                                                end if;
                                        when WRITE_WAIT_ACK =>
                                                if wb_inputs.ack = '1' then
                                                        wb_outputs.cyc <= '0';
                                                        wb_outputs.stb <= '0';
                                                        wb_outputs.we <= '0';
                                                        state <= IDLE;
                                                end if;
                                end case;
                        end if;
                end if;
        end process wishbone;
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	2	skordal	`-- The Potato Processor - A simple processor for FPGAs`
2			`-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>`
3	3	skordal	`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4	2	skordal
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.numeric_std.all;`
8
9	44	skordal	`use work.pp_types.all;`
10			`use work.pp_utilities.all;`
11
12	2	skordal	`--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.`
13			`entity pp_wb_adapter is`
14			`port(`
15			`clk : in std_logic;`
16			`reset : in std_logic;`
17
18			`-- Processor data memory signals:`
19			`signal dmem_address : in std_logic_vector(31 downto 0);`
20			`signal dmem_data_in : in std_logic_vector(31 downto 0); -- Data in to the bus`
21			`signal dmem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus`
22			`signal dmem_data_size : in std_logic_vector( 1 downto 0);`
23			`signal dmem_read_req : in std_logic;`
24			`signal dmem_read_ack : out std_logic;`
25			`signal dmem_write_req : in std_logic;`
26			`signal dmem_write_ack : out std_logic;`
27
28			`-- Wishbone interface:`
29	44	skordal	`wb_inputs : in wishbone_master_inputs;`
30			`wb_outputs : out wishbone_master_outputs`
31	2	skordal	`);`
32			`end entity pp_wb_adapter;`
33
34			`architecture behaviour of pp_wb_adapter is`
35
36	44	skordal	`type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);`
37	2	skordal	`signal state : states;`
38
39			`signal dmem_r_ack : std_logic;`
40
41			`function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)`
42			`return natural is`
43			`begin`
44			`case size is`
45			`when b"01" =>`
46			`case address(1 downto 0) is`
47			`when b"00" =>`
48			`return 0;`
49			`when b"01" =>`
50			`return 8;`
51			`when b"10" =>`
52			`return 16;`
53			`when b"11" =>`
54			`return 24;`
55			`when others =>`
56			`return 0;`
57			`end case;`
58			`when b"10" =>`
59			`if address(1) = '0' then`
60			`return 0;`
61			`else`
62			`return 16;`
63			`end if;`
64			`when others =>`
65			`return 0;`
66			`end case;`
67			`end function get_data_shift;`
68
69			`begin`
70
71	44	skordal	`dmem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';`
72	2	skordal	`dmem_read_ack <= dmem_r_ack;`
73
74			`wishbone: process(clk)`
75			`begin`
76			`if rising_edge(clk) then`
77			`if reset = '1' then`
78			`state <= IDLE;`
79	44	skordal	`wb_outputs.cyc <= '0';`
80			`wb_outputs.stb <= '0';`
81	2	skordal	`dmem_r_ack <= '0';`
82			`else`
83			`case state is`
84			`when IDLE =>`
85			`dmem_r_ack <= '0';`
86
87			`-- Prioritize requests from the data memory:`
88			`if dmem_write_req = '1' then`
89	44	skordal	`wb_outputs.adr <= dmem_address;`
90			`wb_outputs.dat <= std_logic_vector(shift_left(unsigned(dmem_data_in),`
91	2	skordal	`get_data_shift(dmem_data_size, dmem_address)));`
92	44	skordal	`wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);`
93			`wb_outputs.cyc <= '1';`
94			`wb_outputs.stb <= '1';`
95			`wb_outputs.we <= '1';`
96	2	skordal	`state <= WRITE_WAIT_ACK;`
97	44	skordal	`elsif dmem_read_req = '1' then`
98			`wb_outputs.adr <= dmem_address;`
99			`wb_outputs.sel <= wb_get_data_sel(dmem_data_size, dmem_address);`
100			`wb_outputs.cyc <= '1';`
101			`wb_outputs.stb <= '1';`
102			`wb_outputs.we <= '0';`
103	2	skordal	`state <= READ_WAIT_ACK;`
104			`end if;`
105			`when READ_WAIT_ACK =>`
106	44	skordal	`if wb_inputs.ack = '1' then`
107			`dmem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),`
108	2	skordal	`get_data_shift(dmem_data_size, dmem_address)));`
109	44	skordal	`wb_outputs.cyc <= '0';`
110			`wb_outputs.stb <= '0';`
111	2	skordal	`dmem_r_ack <= '1';`
112			`state <= IDLE;`
113			`end if;`
114	44	skordal	`when WRITE_WAIT_ACK =>`
115			`if wb_inputs.ack = '1' then`
116			`wb_outputs.cyc <= '0';`
117			`wb_outputs.stb <= '0';`
118			`wb_outputs.we <= '0';`
119	2	skordal	`state <= IDLE;`
120			`end if;`
121			`end case;`
122			`end if;`
123			`end if;`
124			`end process wishbone;`
125
126			`end architecture behaviour;`

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[/] [potato/] [trunk/] [src/] [pp_wb_adapter.vhd] - Blame information for rev 45