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-----------------------------------------------------------------------
----                                                               ----
---- Present - a lightweight block cipher project                  ----
----                                                               ----
---- This file is part of the Present - a lightweight block        ----
---- cipher project                                                ----
---- http://www.http://opencores.org/project,present               ----
----                                                               ----
---- Description:                                                  ----
----     Test bench of Present encoder with 32 bit IO.             ----
---- To Do:                                                        ----
----                                                               ----
---- Author(s):                                                    ----
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
----                       k.gajewski@gmail.com                    ----
----                                                               ----
-----------------------------------------------------------------------
----                                                               ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
----                                                               ----
---- This source file may be used and distributed without          ----
---- restriction provided that this copyright statement is not     ----
---- removed from the file and that any derivative work contains   ----
---- the original copyright notice and the associated disclaimer.  ----
----                                                               ----
---- This source file is free software; you can redistribute it    ----
---- and-or modify it under the terms of the GNU Lesser General    ----
---- Public License as published by the Free Software Foundation;  ----
---- either version 2.1 of the License, or (at your option) any    ----
---- later version.                                                ----
----                                                               ----
---- This source is distributed in the hope that it will be        ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
---- PURPOSE. See the GNU Lesser General Public License for more   ----
---- details.                                                      ----
----                                                               ----
---- You should have received a copy of the GNU Lesser General     ----
---- Public License along with this source; if not, download it    ----
---- from http://www.opencores.org/lgpl.shtml                      ----
----                                                               ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE std.textio.all;
USE work.txt_util.all;
USE ieee.std_logic_textio.all;
use work.kody.ALL;
 
ENTITY PresentEncTB IS
END PresentEncTB;
 
ARCHITECTURE behavior OF PresentEncTB IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT PresentEnc
    PORT(
         input : IN  std_logic_vector(31 downto 0);
         output : OUT  std_logic_vector(31 downto 0);
         ctrl : IN  std_logic_vector(3 downto 0);
         clk : IN  std_logic;
         reset : IN  std_logic;
         ready : out  std_logic
        );
    END COMPONENT;
 
        -- Clock period definitions
   constant clk_period : time := 1ns;
        constant p10 : time := clk_period/10;
        constant edge : time := clk_period-p10;
 
   --Inputs
   signal input : std_logic_vector(31 downto 0) := (others => '0');
   signal ctrl : std_logic_vector(3 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
        signal strobe : std_logic;
 
        --Outputs
   signal output : std_logic_vector(31 downto 0);
        signal ready : std_logic := '0';
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: PresentEnc PORT MAP (
          input => input,
          output => output,
          ctrl => ctrl,
          clk => clk,
          reset => reset,
          ready => ready
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
 
        file infile :text is in "input.txt";
        variable line_in :line;
        variable bytes : std_logic_vector(32 downto 0);
        variable bytes2 : std_logic_vector(3 downto 0);
        variable xbit : std_logic;
 
 
   begin
      -- hold reset state for 100ms.
      wait for 100ns;
                reset <= '1';
                wait for 10ns;
                reset <= '0';
                wait for 10ns;
      -- insert stimulus here 
                        while not (endfile(infile)) loop
                                readline(infile, line_in);              --2
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                wait for clk_period;
                                readline(infile, line_in);              -- 1
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                readline(infile, line_in);
                                read(line_in, xbit);
                                input <= (others => xbit);
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                readline(infile, line_in);
                                read(line_in, xbit);
                                input <= (others => xbit);
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                readline(infile, line_in);
                                read(line_in, xbit);
                                input <= (others => xbit);
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                readline(infile, line_in);
                                read(line_in, xbit);
                                input <= (others => xbit);
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                readline(infile, line_in);
                                read(line_in, xbit);
                                input <= (others => xbit);
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                wait for clk_period*33;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                wait for clk_period;
                                readline(infile, line_in);
                                hread(line_in, bytes2);
                                ctrl <= bytes2;
                                wait for clk_period*2;
                        end loop;
                assert false severity failure;
   end process;
 
        strobe <= TRANSPORT clk AFTER edge;
 
        outs: PROCESS (strobe)
                variable str :string(1 to 29);
                variable lineout :line;
                variable init_file :std_logic := '1';
                file outfile :text is out "output.txt";
 
                -------- conversion function: std_logic_vector => character --------
                function conv_to_hex_char (sig: std_logic_vector(3 downto 0)) RETURN character IS
                        begin
                        case sig is
                                when "0000" => return '0';
                                when "0001" => return '1';
                                when "0010" => return '2';
                                when "0011" => return '3';
                                when "0100" => return '4';
                                when "0101" => return '5';
                                when "0110" => return '6';
                                when "0111" => return '7';
                                when "1000" => return '8';
                                when "1001" => return '9';
                                when "1010" => return 'A';
                                when "1011" => return 'B';
                                when "1100" => return 'C';
                                when "1101" => return 'D';
                                when "1110" => return 'E';
                                when others => return 'F';
                        end case;
                end conv_to_hex_char;
 
                -------- conversion function: std_logic => character --------
                function conv_to_char (sig: std_logic) RETURN character IS
                        begin
                        case sig is
                                when '1' => return '1';
                                when '0' => return '0';
                                when 'Z' => return 'Z';
                                when others => return 'X';
                        end case;
                end conv_to_char;
 
                -------- conversion function: std_logic_vector => string --------
                function conv_to_string (inp: std_logic_vector; length: integer) RETURN string IS
                        variable x : integer := length/4;
                        variable s : string(1 to x);
                        begin
                                for i in 0 to (x-1) loop
                                s(x-i) := conv_to_hex_char(inp(4*i+3 downto 4*i));
                                end loop;
                        return s;
                end conv_to_string;
 
                -------------------------------------
                begin
                -------- output file header (columns) --------
                        if init_file = '1' then
                                str:="clk                          ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| reset                      ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| | ready                    ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| | | ctrl                   ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| | | | input                ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| | | | |        output      ";
                                write(lineout,str); writeline(outfile,lineout);
                                str:="| | | | |        |           ";
                                write(lineout,str); writeline(outfile,lineout);
                                init_file := '0';
                        end if;
 
                -------- write to output �output� --------
                        if (strobe'EVENT and strobe='0') then
                                str := (others => ' ');
                                str(1) := conv_to_char(clk);
                                str(2) := '|';
                                str(3) := conv_to_char(reset);
                                str(4) := '|';
                                str(5) := conv_to_char(ready);
                                str(6) := '|';
                                str(7) := conv_to_hex_char(ctrl);
                                str(8) := '|';
                                str(9 to 16) := conv_to_string(input,32);
                                str(17) := '|';
                                str(18 to 25) := conv_to_string(output,32);
                                str(26) := '|';
                                write(lineout,str);
                                writeline(outfile,lineout);
                        end if;
        end process outs;
end;

Line No.	Rev	Author	Line
1	4	gajos	`-----------------------------------------------------------------------`
2			`---- ----`
3			`---- Present - a lightweight block cipher project ----`
4			`---- ----`
5			`---- This file is part of the Present - a lightweight block ----`
6			`---- cipher project ----`
7			`---- http://www.http://opencores.org/project,present ----`
8			`---- ----`
9			`---- Description: ----`
10			`---- Test bench of Present encoder with 32 bit IO. ----`
11			`---- To Do: ----`
12			`---- ----`
13			`---- Author(s): ----`
14			`---- - Krzysztof Gajewski, gajos@opencores.org ----`
15			`---- k.gajewski@gmail.com ----`
16			`---- ----`
17			`-----------------------------------------------------------------------`
18			`---- ----`
19			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
20			`---- ----`
21			`---- This source file may be used and distributed without ----`
22			`---- restriction provided that this copyright statement is not ----`
23			`---- removed from the file and that any derivative work contains ----`
24			`---- the original copyright notice and the associated disclaimer. ----`
25			`---- ----`
26			`---- This source file is free software; you can redistribute it ----`
27			`---- and-or modify it under the terms of the GNU Lesser General ----`
28			`---- Public License as published by the Free Software Foundation; ----`
29			`---- either version 2.1 of the License, or (at your option) any ----`
30			`---- later version. ----`
31			`---- ----`
32			`---- This source is distributed in the hope that it will be ----`
33			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
34			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
35			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
36			`---- details. ----`
37			`---- ----`
38			`---- You should have received a copy of the GNU Lesser General ----`
39			`---- Public License along with this source; if not, download it ----`
40			`---- from http://www.opencores.org/lgpl.shtml ----`
41			`---- ----`
42			`-----------------------------------------------------------------------`
43	2	gajos	`LIBRARY ieee;`
44			`USE ieee.std_logic_1164.ALL;`
45			`USE ieee.std_logic_unsigned.all;`
46			`USE ieee.numeric_std.ALL;`
47			`USE std.textio.all;`
48			`USE work.txt_util.all;`
49			`USE ieee.std_logic_textio.all;`
50			`use work.kody.ALL;`
51
52			`ENTITY PresentEncTB IS`
53			`END PresentEncTB;`
54
55			`ARCHITECTURE behavior OF PresentEncTB IS`
56
57			`-- Component Declaration for the Unit Under Test (UUT)`
58
59			`COMPONENT PresentEnc`
60			`PORT(`
61			`input : IN std_logic_vector(31 downto 0);`
62			`output : OUT std_logic_vector(31 downto 0);`
63			`ctrl : IN std_logic_vector(3 downto 0);`
64			`clk : IN std_logic;`
65			`reset : IN std_logic;`
66			`ready : out std_logic`
67			`);`
68			`END COMPONENT;`
69
70			`-- Clock period definitions`
71			`constant clk_period : time := 1ns;`
72			`constant p10 : time := clk_period/10;`
73			`constant edge : time := clk_period-p10;`
74
75			`--Inputs`
76			`signal input : std_logic_vector(31 downto 0) := (others => '0');`
77			`signal ctrl : std_logic_vector(3 downto 0) := (others => '0');`
78			`signal clk : std_logic := '0';`
79			`signal reset : std_logic := '0';`
80			`signal strobe : std_logic;`
81
82			`--Outputs`
83			`signal output : std_logic_vector(31 downto 0);`
84			`signal ready : std_logic := '0';`
85
86			`BEGIN`
87
88			`-- Instantiate the Unit Under Test (UUT)`
89			`uut: PresentEnc PORT MAP (`
90			`input => input,`
91			`output => output,`
92			`ctrl => ctrl,`
93			`clk => clk,`
94			`reset => reset,`
95			`ready => ready`
96			`);`
97
98			`-- Clock process definitions`
99			`clk_process :process`
100			`begin`
101			`clk <= '0';`
102			`wait for clk_period/2;`
103			`clk <= '1';`
104			`wait for clk_period/2;`
105			`end process;`
106
107
108			`-- Stimulus process`
109			`stim_proc: process`
110
111	5	gajos	`file infile :text is in "input.txt";`
112	2	gajos	`variable line_in :line;`
113			`variable bytes : std_logic_vector(32 downto 0);`
114			`variable bytes2 : std_logic_vector(3 downto 0);`
115			`variable xbit : std_logic;`
116
117
118			`begin`
119			`-- hold reset state for 100ms.`
120			`wait for 100ns;`
121			`reset <= '1';`
122			`wait for 10ns;`
123			`reset <= '0';`
124			`wait for 10ns;`
125			`-- insert stimulus here`
126			`while not (endfile(infile)) loop`
127			`readline(infile, line_in); --2`
128			`hread(line_in, bytes2);`
129			`ctrl <= bytes2;`
130			`wait for clk_period;`
131			`readline(infile, line_in); -- 1`
132			`hread(line_in, bytes2);`
133			`ctrl <= bytes2;`
134			`readline(infile, line_in);`
135			`read(line_in, xbit);`
136			`input <= (others => xbit);`
137			`wait for clk_period;`
138			`readline(infile, line_in);`
139			`hread(line_in, bytes2);`
140			`ctrl <= bytes2;`
141			`readline(infile, line_in);`
142			`read(line_in, xbit);`
143			`input <= (others => xbit);`
144			`wait for clk_period;`
145			`readline(infile, line_in);`
146			`hread(line_in, bytes2);`
147			`ctrl <= bytes2;`
148			`readline(infile, line_in);`
149			`read(line_in, xbit);`
150			`input <= (others => xbit);`
151			`wait for clk_period;`
152			`readline(infile, line_in);`
153			`hread(line_in, bytes2);`
154			`ctrl <= bytes2;`
155			`readline(infile, line_in);`
156			`read(line_in, xbit);`
157			`input <= (others => xbit);`
158			`wait for clk_period;`
159			`readline(infile, line_in);`
160			`hread(line_in, bytes2);`
161			`ctrl <= bytes2;`
162			`readline(infile, line_in);`
163			`read(line_in, xbit);`
164			`input <= (others => xbit);`
165			`wait for clk_period;`
166			`readline(infile, line_in);`
167			`hread(line_in, bytes2);`
168			`ctrl <= bytes2;`
169			`wait for clk_period*33;`
170			`readline(infile, line_in);`
171			`hread(line_in, bytes2);`
172			`ctrl <= bytes2;`
173			`wait for clk_period;`
174			`readline(infile, line_in);`
175			`hread(line_in, bytes2);`
176			`ctrl <= bytes2;`
177			`wait for clk_period*2;`
178			`end loop;`
179			`assert false severity failure;`
180			`end process;`
181
182			`strobe <= TRANSPORT clk AFTER edge;`
183
184			`outs: PROCESS (strobe)`
185			`variable str :string(1 to 29);`
186			`variable lineout :line;`
187			`variable init_file :std_logic := '1';`
188	5	gajos	`file outfile :text is out "output.txt";`
189	2	gajos
190	5	gajos	`-------- conversion function: std_logic_vector => character --------`
191	2	gajos	`function conv_to_hex_char (sig: std_logic_vector(3 downto 0)) RETURN character IS`
192			`begin`
193			`case sig is`
194			`when "0000" => return '0';`
195			`when "0001" => return '1';`
196			`when "0010" => return '2';`
197			`when "0011" => return '3';`
198			`when "0100" => return '4';`
199			`when "0101" => return '5';`
200			`when "0110" => return '6';`
201			`when "0111" => return '7';`
202			`when "1000" => return '8';`
203			`when "1001" => return '9';`
204			`when "1010" => return 'A';`
205			`when "1011" => return 'B';`
206			`when "1100" => return 'C';`
207			`when "1101" => return 'D';`
208			`when "1110" => return 'E';`
209			`when others => return 'F';`
210			`end case;`
211			`end conv_to_hex_char;`
212
213	5	gajos	`-------- conversion function: std_logic => character --------`
214	2	gajos	`function conv_to_char (sig: std_logic) RETURN character IS`
215			`begin`
216			`case sig is`
217			`when '1' => return '1';`
218			`when '0' => return '0';`
219			`when 'Z' => return 'Z';`
220			`when others => return 'X';`
221			`end case;`
222			`end conv_to_char;`
223
224	5	gajos	`-------- conversion function: std_logic_vector => string --------`
225	2	gajos	`function conv_to_string (inp: std_logic_vector; length: integer) RETURN string IS`
226			`variable x : integer := length/4;`
227			`variable s : string(1 to x);`
228			`begin`
229			`for i in 0 to (x-1) loop`
230			`s(x-i) := conv_to_hex_char(inp(4i+3 downto 4i));`
231			`end loop;`
232			`return s;`
233			`end conv_to_string;`
234
235			`-------------------------------------`
236			`begin`
237	5	gajos	`-------- output file header (columns) --------`
238	2	gajos	`if init_file = '1' then`
239			`str:="clk ";`
240			`write(lineout,str); writeline(outfile,lineout);`
241			`str:="\| reset ";`
242			`write(lineout,str); writeline(outfile,lineout);`
243			`str:="\| \| ready ";`
244			`write(lineout,str); writeline(outfile,lineout);`
245			`str:="\| \| \| ctrl ";`
246			`write(lineout,str); writeline(outfile,lineout);`
247			`str:="\| \| \| \| input ";`
248			`write(lineout,str); writeline(outfile,lineout);`
249			`str:="\| \| \| \| \| output ";`
250			`write(lineout,str); writeline(outfile,lineout);`
251			`str:="\| \| \| \| \| \| ";`
252			`write(lineout,str); writeline(outfile,lineout);`
253			`init_file := '0';`
254			`end if;`
255
256	5	gajos	`-------- write to output �output� --------`
257	2	gajos	`if (strobe'EVENT and strobe='0') then`
258			`str := (others => ' ');`
259			`str(1) := conv_to_char(clk);`
260			`str(2) := '\|';`
261			`str(3) := conv_to_char(reset);`
262			`str(4) := '\|';`
263			`str(5) := conv_to_char(ready);`
264			`str(6) := '\|';`
265			`str(7) := conv_to_hex_char(ctrl);`
266			`str(8) := '\|';`
267			`str(9 to 16) := conv_to_string(input,32);`
268			`str(17) := '\|';`
269			`str(18 to 25) := conv_to_string(output,32);`
270			`str(26) := '\|';`
271			`write(lineout,str);`
272			`writeline(outfile,lineout);`
273			`end if;`
274			`end process outs;`
275			`end;`

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[/] [present/] [trunk/] [32BitIO/] [bench/] [vhdl/] [PresentEncTB.vhd] - Blame information for rev 5