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[/] [present/] [trunk/] [32BitIO/] [rtl/] [vhdl/] [PresentEnc.vhd] - Blame information for rev 4

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1 4 gajos 
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     Top level of present encoder with 32 bit IO.              ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
43 2 gajos 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity PresentEnc is
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        generic (
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                        w_2: integer := 2;
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                        w_4: integer := 4;
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                        w_5: integer := 5;
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                        w_32: integer := 32;
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                        w_64: integer := 64;
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                        w_80: integer := 80
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        );
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        port(
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                ctrl    : in std_logic_vector(w_4-1 downto 0);
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                input : in std_logic_vector(w_32-1 downto 0);
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                output : out std_logic_vector(w_32-1 downto 0);
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                clk, reset : in std_logic;
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                ready : out std_logic
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        );
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end PresentEnc;
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architecture Behavioral of PresentEnc is
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        component PresentStateMachine is
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                generic (
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                        w_2: integer := 2;
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                        w_4: integer := 4;
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                        w_5: integer := 5;
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                        w_32: integer := 32;
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                        w_64: integer := 64;
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                        w_80: integer := 80
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                );
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                port (
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                        info : in std_logic_vector (w_2-1 downto 0);
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                        ctrl : in std_logic_vector (w_4-1 downto 0);
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                        key_ctrl: out std_logic_vector (w_2-1 downto 0);
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                        plain_ctrl: out std_logic_vector (w_2-1 downto 0);
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                        outReg : out std_logic_vector (w_2-1 downto 0);
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                        reset, clk : in std_logic;
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                        ready, cnt_res, ctrl_mux64, ctrl_mux80 : out std_logic
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                );
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        end component;
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89 4 gajos 
        -- substitution layer for decoding
90 2 gajos 
        component slayer is
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                generic (
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                                w_4 : integer := 4
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                );
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                port (
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                        input : in std_logic_vector(w_4-1 downto 0);
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                        output : out std_logic_vector(w_4-1 downto 0)
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                );
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        end component;
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100 4 gajos 
        -- permutation layer for decoding
101 2 gajos 
        component pLayer is
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                generic(w_64 : integer := 64);
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                port(
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                        input : in std_logic_vector(w_64-1 downto 0);
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                        output : out std_logic_vector(w_64-1 downto 0)
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                );
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        end component;
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109 4 gajos 
        -- key update for decoding
110 2 gajos 
        component keyupd is
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                generic(
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                        w_5 : integer := 5;
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                        w_80: integer := 80
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                );
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                port(
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                        num : in std_logic_vector(w_5-1 downto 0);
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                        key : in std_logic_vector(w_80-1 downto 0);
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                        keyout : out std_logic_vector(w_80-1 downto 0)
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                );
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        end component;
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122 4 gajos 
        -- 'register' for 32 bit output and 64 bit input
123 2 gajos 
        component outputRegister is
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                generic (
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                        w_2 : integer := 2;
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                        w_32: integer := 32;
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                        w_64: integer := 64
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                );
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                port(
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                        ctrl : in std_logic_vector(w_2-1 downto 0);
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                        input : in std_logic_vector(w_64-1 downto 0);
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                        output : out std_logic_vector(w_32-1 downto 0);
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                        rst, clk, rd : in std_logic;
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                        ready : out std_logic
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                );
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        end component;
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138 4 gajos 
        -- counter for decoding. It is counting up!!!
139 2 gajos 
        component counter is
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                generic (
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                        w_2 : integer := 2;
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                        w_5 : integer := 5
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                );
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                port (
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                        clk, reset, cnt_res : in std_logic;
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                        info : out std_logic_vector(w_2-1 downto 0);
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                        num : out std_logic_vector (w_5-1 downto 0)
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                );
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        end component;
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151 4 gajos 
        -- 'multiplexer' for 32/64 bit input and 64 bit output
152 2 gajos 
        component mux64 is
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                generic (
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                        w_2 : integer := 2;
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                        w_32 : integer := 32;
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                        w_64 : integer := 64
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                        );
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                port(
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                        i0ctrl : in std_logic_vector (w_2-1 downto 0);
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                        input0 : in std_logic_vector(w_32-1 downto 0);
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                        input1 : in std_logic_vector(w_64-1 downto 0);
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                        output : inout std_logic_vector(w_64-1 downto 0);
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                        ctrl, clk, reset : in std_logic
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                );
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        end component;
166 
 
167 4 gajos 
        -- 'multiplexer' for 32/80 bit input and 80 bit output
168 2 gajos 
        component mux80 is
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                generic (
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                        w_2 : integer := 2;
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                        w_32 : integer := 32;
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                        w_80 : integer := 80
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                        );
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                port(
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                        i0ctrl : in std_logic_vector (w_2-1 downto 0);
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                        input0 : in std_logic_vector(w_32-1 downto 0);
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                        input1 : in std_logic_vector(w_80-1 downto 0);
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                        output : inout std_logic_vector(w_80-1 downto 0);
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                        ctrl, clk, reset : in std_logic
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                );
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        end component;
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        component xorModule is
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                generic(
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                        w : positive
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                );
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                port(
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                        inputA, inputB : in std_logic_vector( w-1 downto 0 );
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                        output : out std_logic_vector ( w-1 downto 0 )
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                );
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        end component;
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193 4 gajos 
        -- signals
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195 2 gajos 
        signal ro32ctrl, key_ctrl, plain_ctrl, info : std_logic_vector(w_2-1 downto 0);
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        signal keynum : std_logic_vector (w_5-1 downto 0);
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        signal toXor, ciphertext, P, Pout : std_logic_vector (w_64-1 downto 0);
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        signal keyfout, kupd : std_logic_vector (w_80-1 downto 0);
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        signal ready_sig, mux64ctrl, mux80ctrl, cnt_res : std_logic;
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        begin
202 4 gajos 
 
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            -- connections
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205 2 gajos 
                mux_64: mux64 port map(
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                        input0 => input, input1 => Pout, output => toXor, ctrl => mux64ctrl,
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                        i0ctrl => plain_ctrl, clk => clk, reset => reset);
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                mux_80: mux80 port map(
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                        input0 => input, input1 => kupd, output => keyfout, ctrl => mux80ctrl,
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                        i0ctrl => key_ctrl, clk => clk, reset => reset);
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                slayers : for N in 15 downto 0 generate
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                        s_x: slayer port map(input => ciphertext(4*N+3 downto 4*N), output => P(4*N+3 downto 4*N));
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                end generate slayers;
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                p1: pLayer port map(input => P, output => Pout);
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                mixer: keyupd port map(key => keyfout, num => keynum, keyout => kupd);
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                output_reg: outputRegister port map(rst => reset, clk => clk, rd => ready_sig, ctrl => ro32ctrl,
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                        input => ciphertext, output => output, ready => ready);
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                SM: PresentStateMachine port map(ctrl => ctrl, outReg => ro32ctrl, reset => reset,
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                        ready => ready_sig, cnt_res => cnt_res, ctrl_mux64 => mux64ctrl, ctrl_mux80 => mux80ctrl,
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                        clk => clk, key_ctrl => key_ctrl,  plain_ctrl => plain_ctrl, info => info
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                        );
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                count: counter port map( clk => clk, reset => reset, cnt_res => cnt_res, info => info, num => keynum);
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                ciphertext <= toXor xor keyfout(79 downto 16);
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end Behavioral;

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