OpenCores
URL https://opencores.org/ocsvn/present/present/trunk

Subversion Repositories present

[/] [present/] [trunk/] [Pure/] [rtl/] [vhdl/] [Reg.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 gajos
-----------------------------------------------------------------------
2
----                                                               ----
3
---- Present - a lightweight block cipher project                  ----
4
----                                                               ----
5
---- This file is part of the Present - a lightweight block        ----
6
---- cipher project                                                ----
7
---- http://www.http://opencores.org/project,present               ----
8
----                                                               ----
9
---- Description:                                                  ----
10
----     Register - nothing special.                                ----
11
---- To Do:                                                        ----
12
----                                                               ----
13
---- Author(s):                                                    ----
14
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
15
----                       k.gajewski@gmail.com                    ----
16
----                                                               ----
17
-----------------------------------------------------------------------
18
----                                                               ----
19
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
20
----                                                               ----
21
---- This source file may be used and distributed without          ----
22
---- restriction provided that this copyright statement is not     ----
23
---- removed from the file and that any derivative work contains   ----
24
---- the original copyright notice and the associated disclaimer.  ----
25
----                                                               ----
26
---- This source file is free software; you can redistribute it    ----
27
---- and-or modify it under the terms of the GNU Lesser General    ----
28
---- Public License as published by the Free Software Foundation;  ----
29
---- either version 2.1 of the License, or (at your option) any    ----
30
---- later version.                                                ----
31
----                                                               ----
32
---- This source is distributed in the hope that it will be        ----
33
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
34
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
35
---- PURPOSE. See the GNU Lesser General Public License for more   ----
36
---- details.                                                      ----
37
----                                                               ----
38
---- You should have received a copy of the GNU Lesser General     ----
39
---- Public License along with this source; if not, download it    ----
40
---- from http://www.opencores.org/lgpl.shtml                      ----
41
----                                                               ----
42
-----------------------------------------------------------------------
43 3 gajos
library IEEE;
44
use IEEE.STD_LOGIC_1164.ALL;
45
 
46
-- Uncomment the following library declaration if using
47
-- arithmetic functions with Signed or Unsigned values
48
--use IEEE.NUMERIC_STD.ALL;
49
 
50
-- Uncomment the following library declaration if instantiating
51
-- any Xilinx primitives in this code.
52
--library UNISIM;
53
--use UNISIM.VComponents.all;
54
 
55
entity Reg is
56
        generic(width : integer := 64);
57
        port(
58
                input  : in  STD_LOGIC_VECTOR(width - 1 downto 0);
59
                output : out STD_LOGIC_VECTOR(width - 1 downto 0);
60
                enable : in  STD_LOGIC;
61
                clk    : in  STD_LOGIC;
62
                reset  : in  STD_LOGIC
63
        );
64
end Reg;
65
 
66
architecture Behavioral of Reg is
67
 
68
signal reg : STD_LOGIC_VECTOR(width - 1 downto 0);
69
 
70
begin
71
        clock : process(clk, reset)
72
                begin
73
                        if (reset = '1') then
74
                                reg <= (others => '0');
75
                        elsif (clk = '1' and clk'Event) then
76
                                if (enable = '1') then
77
                                        reg <= input;
78
                                end if;
79
                        end if;
80
                end process clock;
81
        output <= reg;
82
end Behavioral;
83
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.