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`timescale 1ns / 1ps
//=============================================================================
//      (C) 2007,2012  Robert Finch
//  robfinch<remove>@opencores.org
//      All rights reserved.
//
//      PSGBusArb.v
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//              Arbitrates access to the system bus among up to eight
//      wave table channels for the PSG. This arbitrator is part
//      of a tree that ends up looking like a single arbitration
//      request to the system.
//
//      Spartan3
//      19 LUTs / 11 slices
//=============================================================================
 
module PSGBusArb(rst, clk, ce, ack,
        req0, req1, req2, req3, req4, req5, req6, req7,
        sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, seln);
input rst;              // reset
input clk;              // clock (eg 100MHz)
input ce;               // clock enable (eg 25MHz)
input ack;              // bus transfer completed
input req0;             // requester 0 wants the bus
input req1;             // requester 1 wants the bus
input req2;             // ...
input req3;
input req4;
input req5;
input req6;
input req7;
output sel0;    // requester 0 granted the bus
reg sel0;
output sel1;
reg sel1;
output sel2;
reg sel2;
output sel3;
reg sel3;
output sel4;
reg sel4;
output sel5;
reg sel5;
output sel6;
reg sel6;
output sel7;
reg sel7;
output [2:0] seln;       // who has the bus
reg [2:0] seln;
 
always @(posedge clk) begin
        if (rst) begin
                sel0 <= 1'b0;
                sel1 <= 1'b0;
                sel2 <= 1'b0;
                sel3 <= 1'b0;
                sel4 <= 1'b0;
                sel5 <= 1'b0;
                sel6 <= 1'b0;
                sel7 <= 1'b0;
                seln <= 3'd0;
        end
        else begin
                if (ce&ack) begin
                        if (req0) begin
                                sel0 <= 1'b1;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd0;
                        end
                        else if (req1) begin
                                sel1 <= 1'b1;
                                sel0 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd1;
                        end
                        else if (req2) begin
                                sel2 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd2;
                        end
                        else if (req3) begin
                                sel3 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd3;
                        end
                        else if (req4) begin
                                sel4 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd4;
                        end
                        else if (req5) begin
                                sel5 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel6 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd5;
                        end
                        else if (req6) begin
                                sel6 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel7 <= 1'b0;
                                seln <= 3'd6;
                        end
                        else if (req7) begin
                                sel7 <= 1'b1;
                                sel0 <= 1'b0;
                                sel1 <= 1'b0;
                                sel2 <= 1'b0;
                                sel3 <= 1'b0;
                                sel4 <= 1'b0;
                                sel5 <= 1'b0;
                                sel6 <= 1'b0;
                                seln <= 3'd7;
                        end
                        // otherwise, hold onto last owner
                        else begin
                                sel0 <= sel0;
                                sel1 <= sel1;
                                sel2 <= sel2;
                                sel3 <= sel3;
                                sel4 <= sel4;
                                sel5 <= sel5;
                                sel6 <= sel6;
                                sel7 <= sel7;
                                seln <= seln;
                        end
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`timescale 1ns / 1ps
2			`//=============================================================================`
3			`// (C) 2007,2012 Robert Finch`
4			`// robfinch<remove>@opencores.org`
5			`// All rights reserved.`
6			`//`
7			`// PSGBusArb.v`
8			`//`
9			`// This source file is free software: you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation, either version 3 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source file is distributed in the hope that it will be useful,`
15			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
16			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
17			`// GNU General Public License for more details.`
18			`//`
19			`// You should have received a copy of the GNU General Public License`
20			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
21			`//`
22			`// Arbitrates access to the system bus among up to eight`
23			`// wave table channels for the PSG. This arbitrator is part`
24			`// of a tree that ends up looking like a single arbitration`
25			`// request to the system.`
26			`//`
27			`// Spartan3`
28			`// 19 LUTs / 11 slices`
29			`//=============================================================================`
30
31			`module PSGBusArb(rst, clk, ce, ack,`
32			`req0, req1, req2, req3, req4, req5, req6, req7,`
33			`sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, seln);`
34			`input rst; // reset`
35			`input clk; // clock (eg 100MHz)`
36			`input ce; // clock enable (eg 25MHz)`
37			`input ack; // bus transfer completed`
38			`input req0; // requester 0 wants the bus`
39			`input req1; // requester 1 wants the bus`
40			`input req2; // ...`
41			`input req3;`
42			`input req4;`
43			`input req5;`
44			`input req6;`
45			`input req7;`
46			`output sel0; // requester 0 granted the bus`
47			`reg sel0;`
48			`output sel1;`
49			`reg sel1;`
50			`output sel2;`
51			`reg sel2;`
52			`output sel3;`
53			`reg sel3;`
54			`output sel4;`
55			`reg sel4;`
56			`output sel5;`
57			`reg sel5;`
58			`output sel6;`
59			`reg sel6;`
60			`output sel7;`
61			`reg sel7;`
62			`output [2:0] seln; // who has the bus`
63			`reg [2:0] seln;`
64
65			`always @(posedge clk) begin`
66			`if (rst) begin`
67			`sel0 <= 1'b0;`
68			`sel1 <= 1'b0;`
69			`sel2 <= 1'b0;`
70			`sel3 <= 1'b0;`
71			`sel4 <= 1'b0;`
72			`sel5 <= 1'b0;`
73			`sel6 <= 1'b0;`
74			`sel7 <= 1'b0;`
75			`seln <= 3'd0;`
76			`end`
77			`else begin`
78			`if (ce&ack) begin`
79			`if (req0) begin`
80			`sel0 <= 1'b1;`
81			`sel1 <= 1'b0;`
82			`sel2 <= 1'b0;`
83			`sel3 <= 1'b0;`
84			`sel4 <= 1'b0;`
85			`sel5 <= 1'b0;`
86			`sel6 <= 1'b0;`
87			`sel7 <= 1'b0;`
88			`seln <= 3'd0;`
89			`end`
90			`else if (req1) begin`
91			`sel1 <= 1'b1;`
92			`sel0 <= 1'b0;`
93			`sel2 <= 1'b0;`
94			`sel3 <= 1'b0;`
95			`sel4 <= 1'b0;`
96			`sel5 <= 1'b0;`
97			`sel6 <= 1'b0;`
98			`sel7 <= 1'b0;`
99			`seln <= 3'd1;`
100			`end`
101			`else if (req2) begin`
102			`sel2 <= 1'b1;`
103			`sel0 <= 1'b0;`
104			`sel1 <= 1'b0;`
105			`sel3 <= 1'b0;`
106			`sel4 <= 1'b0;`
107			`sel5 <= 1'b0;`
108			`sel6 <= 1'b0;`
109			`sel7 <= 1'b0;`
110			`seln <= 3'd2;`
111			`end`
112			`else if (req3) begin`
113			`sel3 <= 1'b1;`
114			`sel0 <= 1'b0;`
115			`sel1 <= 1'b0;`
116			`sel2 <= 1'b0;`
117			`sel4 <= 1'b0;`
118			`sel5 <= 1'b0;`
119			`sel6 <= 1'b0;`
120			`sel7 <= 1'b0;`
121			`seln <= 3'd3;`
122			`end`
123			`else if (req4) begin`
124			`sel4 <= 1'b1;`
125			`sel0 <= 1'b0;`
126			`sel1 <= 1'b0;`
127			`sel2 <= 1'b0;`
128			`sel3 <= 1'b0;`
129			`sel5 <= 1'b0;`
130			`sel6 <= 1'b0;`
131			`sel7 <= 1'b0;`
132			`seln <= 3'd4;`
133			`end`
134			`else if (req5) begin`
135			`sel5 <= 1'b1;`
136			`sel0 <= 1'b0;`
137			`sel1 <= 1'b0;`
138			`sel2 <= 1'b0;`
139			`sel3 <= 1'b0;`
140			`sel4 <= 1'b0;`
141			`sel6 <= 1'b0;`
142			`sel7 <= 1'b0;`
143			`seln <= 3'd5;`
144			`end`
145			`else if (req6) begin`
146			`sel6 <= 1'b1;`
147			`sel0 <= 1'b0;`
148			`sel1 <= 1'b0;`
149			`sel2 <= 1'b0;`
150			`sel3 <= 1'b0;`
151			`sel4 <= 1'b0;`
152			`sel5 <= 1'b0;`
153			`sel7 <= 1'b0;`
154			`seln <= 3'd6;`
155			`end`
156			`else if (req7) begin`
157			`sel7 <= 1'b1;`
158			`sel0 <= 1'b0;`
159			`sel1 <= 1'b0;`
160			`sel2 <= 1'b0;`
161			`sel3 <= 1'b0;`
162			`sel4 <= 1'b0;`
163			`sel5 <= 1'b0;`
164			`sel6 <= 1'b0;`
165			`seln <= 3'd7;`
166			`end`
167			`// otherwise, hold onto last owner`
168			`else begin`
169			`sel0 <= sel0;`
170			`sel1 <= sel1;`
171			`sel2 <= sel2;`
172			`sel3 <= sel3;`
173			`sel4 <= sel4;`
174			`sel5 <= sel5;`
175			`sel6 <= sel6;`
176			`sel7 <= sel7;`
177			`seln <= seln;`
178			`end`
179			`end`
180			`end`
181			`end`
182
183			`endmodule`

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[/] [psg16/] [trunk/] [rtl/] [verilog/] [PSGBusArb.v] - Blame information for rev 2