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[/] [psg16/] [trunk/] [rtl/] [verilog/] [PSGHarmonicSynthesizer.v] - Blame information for rev 4

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1 4 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2007-2017  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// PSGHarmonicSynthsizer.v
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// Harmonic synthesizer
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//=============================================================================
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module PSGHarmonicSynthesizer(rst, clk, test, sync, freq, o);
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parameter WID = 32;
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input rst;
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input clk;
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input test;
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input sync;
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input [WID-1:0] freq;   // frequency control
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output [WID-1:0] o;
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reg [WID-1:0] acc;
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always @(posedge clk)
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if (rst)
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    acc <= 0;
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else begin
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    if (~test) begin
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        if (sync)
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            acc <= 0;
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        else
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            acc <= acc + freq;
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    end
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    else
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        acc <= 0;
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end
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assign o = acc;
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endmodule

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