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[/] [psg16/] [trunk/] [rtl/] [verilog/] [PSGNoteOutMux.v] - Blame information for rev 2

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1 2 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//      (C) 2007,2012  Robert Finch
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//  robfinch<remove>@opencores.org
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//      All rights reserved.
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//
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//      PSGNoteOutMux.v
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//      Version 1.0
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//      
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//      Selects from one of five waveforms for output. Selected waveform
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//      outputs are anded together. This is approximately how the
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//      original SID worked.
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//
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//      Spartan3
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//      Webpack 9.1i xc3s1000-4ft256
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//      36 LUTs / 21 slices / 11ns
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//============================================================================ */
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//
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module PSGNoteOutMux(s, a, b, c, d, e, o);
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parameter WID = 12;
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input [4:0] s;
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input [WID-1:0] a,b,c,d,e;
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output [WID-1:0] o;
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wire [WID-1:0] o1,o2,o3,o4,o5;
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assign o1 = s[4] ? e : {WID{1'b1}};
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assign o2 = s[3] ? d : {WID{1'b1}};
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assign o3 = s[2] ? c : {WID{1'b1}};
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assign o4 = s[1] ? b : {WID{1'b1}};
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assign o5 = s[0] ? a : {WID{1'b1}};
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assign o = o1 & o2 & o3 & o4 & o5;
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endmodule
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