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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.9
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module pss
#(
        parameter CPU_PRESENT = 1,
        parameter CPU_RESET_DEFAULT = 1,
        parameter A31_DEFAULTS = 1,
        parameter MEM_SIZE_KB = 1,
        parameter MEM_DATA = ""
)
(
        input clk_i, arst_i,
        output srst_o,
 
        input rx_i,
        output tx_o,
 
        input [3:0] INT_i,
 
        // Expansion bus
        output xport_req_o,
        input  xport_ack_i,
        input  xport_err_i,
        output xport_we_o,
        output [31:0] xport_addr_bo,
        output [31:0] xport_wdata_bo,
        input  xport_resp_i,
        input  [31:0] xport_rdata_bi
);
 
wire sync_rst, udm_rst;
as_reset_cntrl as_reset_cntrl
(
        .clk_i(clk_i),
        .rst_i(arst_i),
        .rst_o(sync_rst)
);
 
assign srst_o = sync_rst | udm_rst;
 
wire dbg_bus_enb;
wire dbg_bus_we;
wire [31:0] dbg_bus_addr;
wire [31:0] dbg_bus_wdata;
wire [31:0] dbg_bus_rdata;
wire dbg_bus_resp;
 
udm udm
(
        .clk_i(clk_i),
        .rst_i(sync_rst),
 
        .rx_i(rx_i),
        .tx_o(tx_o),
 
        .rst_o(udm_rst),
        .bus_enb_o(dbg_bus_enb),
        .bus_we_o(dbg_bus_we),
        .bus_addr_bo(dbg_bus_addr),
    .bus_wdata_bo(dbg_bus_wdata),
 
    .bus_ack_i(dbg_bus_resp),
    .bus_rdata_bi(dbg_bus_rdata)
);
 
ZPU_uC
#(
        .CPU_PRESENT(CPU_PRESENT),
        .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
        .A31_DEFAULTS(A31_DEFAULTS),
        .MEM_DATA(MEM_DATA),
        .MEM_SIZE_KB(MEM_SIZE_KB)
)
ZPU_uC
(
        .clk_i(clk_i),
        .rst_i(srst_o),
        .INT_i(INT_i),
 
        // Expansion bus
        .xport_req_o(xport_req_o),
        .xport_ack_i(xport_ack_i),
        .xport_err_i(xport_err_i),
        .xport_we_o(xport_we_o),
        .xport_addr_bo(xport_addr_bo),
        .xport_wdata_bo(xport_wdata_bo),
        .xport_resp_i(xport_resp_i),
        .xport_rdata_bi(xport_rdata_bi),
 
        //Debug interface
        .dbg_enb_i(dbg_bus_enb),
        .dbg_wr_i(dbg_bus_we),
        .dbg_addr_bi(dbg_bus_addr),
        .dbg_data_bi(dbg_bus_wdata),
        .dbg_resp_o(dbg_bus_resp),
        .dbg_data_bo(dbg_bus_rdata)
);
 
endmodule

Line No.	Rev	Author	Line
1	2	AlexAntono	`/*`
2			`PSS`
3
4			`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
5			`All rights reserved.`
6
7			`Version 0.9`
8
9			`The FreeBSD license`
10
11			`Redistribution and use in source and binary forms, with or without`
12			`modification, are permitted provided that the following conditions`
13			`are met:`
14
15			`1. Redistributions of source code must retain the above copyright`
16			`notice, this list of conditions and the following disclaimer.`
17			`2. Redistributions in binary form must reproduce the above`
18			`copyright notice, this list of conditions and the following`
19			`disclaimer in the documentation and/or other materials`
20			`provided with the distribution.`
21
22			THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
23			`EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
24			`THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A`
25			`PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE`
26			`PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,`
27			`INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
28			`(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
29			`OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
30			`HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
31			`STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
32			`ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
33			`ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`*/`
35
36
37			`module pss`
38			`#(`
39			`parameter CPU_PRESENT = 1,`
40			`parameter CPU_RESET_DEFAULT = 1,`
41			`parameter A31_DEFAULTS = 1,`
42			`parameter MEM_SIZE_KB = 1,`
43			`parameter MEM_DATA = ""`
44			`)`
45			`(`
46			`input clk_i, arst_i,`
47			`output srst_o,`
48
49			`input rx_i,`
50			`output tx_o,`
51
52			`input [3:0] INT_i,`
53
54			`// Expansion bus`
55			`output xport_req_o,`
56			`input xport_ack_i,`
57			`input xport_err_i,`
58			`output xport_we_o,`
59			`output [31:0] xport_addr_bo,`
60			`output [31:0] xport_wdata_bo,`
61			`input xport_resp_i,`
62			`input [31:0] xport_rdata_bi`
63			`);`
64
65			`wire sync_rst, udm_rst;`
66			`as_reset_cntrl as_reset_cntrl`
67			`(`
68			`.clk_i(clk_i),`
69			`.rst_i(arst_i),`
70			`.rst_o(sync_rst)`
71			`);`
72
73			`assign srst_o = sync_rst \| udm_rst;`
74
75			`wire dbg_bus_enb;`
76			`wire dbg_bus_we;`
77			`wire [31:0] dbg_bus_addr;`
78			`wire [31:0] dbg_bus_wdata;`
79			`wire [31:0] dbg_bus_rdata;`
80			`wire dbg_bus_resp;`
81
82			`udm udm`
83			`(`
84			`.clk_i(clk_i),`
85			`.rst_i(sync_rst),`
86
87			`.rx_i(rx_i),`
88			`.tx_o(tx_o),`
89
90			`.rst_o(udm_rst),`
91			`.bus_enb_o(dbg_bus_enb),`
92			`.bus_we_o(dbg_bus_we),`
93			`.bus_addr_bo(dbg_bus_addr),`
94			`.bus_wdata_bo(dbg_bus_wdata),`
95
96			`.bus_ack_i(dbg_bus_resp),`
97			`.bus_rdata_bi(dbg_bus_rdata)`
98			`);`
99
100			`ZPU_uC`
101			`#(`
102			`.CPU_PRESENT(CPU_PRESENT),`
103			`.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),`
104			`.A31_DEFAULTS(A31_DEFAULTS),`
105			`.MEM_DATA(MEM_DATA),`
106			`.MEM_SIZE_KB(MEM_SIZE_KB)`
107			`)`
108			`ZPU_uC`
109			`(`
110			`.clk_i(clk_i),`
111			`.rst_i(srst_o),`
112			`.INT_i(INT_i),`
113
114			`// Expansion bus`
115			`.xport_req_o(xport_req_o),`
116			`.xport_ack_i(xport_ack_i),`
117			`.xport_err_i(xport_err_i),`
118			`.xport_we_o(xport_we_o),`
119			`.xport_addr_bo(xport_addr_bo),`
120			`.xport_wdata_bo(xport_wdata_bo),`
121			`.xport_resp_i(xport_resp_i),`
122			`.xport_rdata_bi(xport_rdata_bi),`
123
124			`//Debug interface`
125			`.dbg_enb_i(dbg_bus_enb),`
126			`.dbg_wr_i(dbg_bus_we),`
127			`.dbg_addr_bi(dbg_bus_addr),`
128			`.dbg_data_bi(dbg_bus_wdata),`
129			`.dbg_resp_o(dbg_bus_resp),`
130			`.dbg_data_bo(dbg_bus_rdata)`
131			`);`
132
133			`endmodule`

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