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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [udm/] [uart_rx.v] - Blame information for rev 5

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1 2 AlexAntono
/*
2
 PSS
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 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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 All rights reserved.
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7 5 AlexAntono
 Version 0.99
8 2 AlexAntono
 
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 The FreeBSD license
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 Redistribution and use in source and binary forms, with or without
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 modification, are permitted provided that the following conditions
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 are met:
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 1. Redistributions of source code must retain the above copyright
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    notice, this list of conditions and the following disclaimer.
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 2. Redistributions in binary form must reproduce the above
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    copyright notice, this list of conditions and the following
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    disclaimer in the documentation and/or other materials
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    provided with the distribution.
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 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module uart_rx
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(
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        input clk_i, rst_i,
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        input rx_i,
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        output reg rx_done_tick_o,
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        output reg [7:0] dout_bo,
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        output reg locked_o,
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        output reg [28:0] bitperiod_o
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);
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localparam ST_NOSYNC                    = 4'h0;
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localparam ST_NOSYNC_WAIT1_1    = 4'h1;
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localparam ST_NOSYNC_WAIT0_2    = 4'h2;
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localparam ST_NOSYNC_WAIT1_3    = 4'h3;
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localparam ST_NOSYNC_WAIT0_4    = 4'h4;
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localparam ST_NOSYNC_WAIT1_5    = 4'h5;
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localparam ST_NOSYNC_WAIT0_6    = 4'h6;
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localparam ST_NOSYNC_WAIT1_7    = 4'h7;
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localparam ST_NOSYNC_WAIT0_8    = 4'h8;
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localparam ST_NOSYNC_WAIT_STOP  = 4'h9;
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localparam ST_SYNC                              = 4'hA;
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localparam ST_SYNC_WAIT_START   = 4'hB;
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localparam ST_SYNC_RX_DATA              = 4'hC;
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localparam ST_SYNC_WAIT_STOP    = 4'hD;
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reg [4:0]        state;
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reg [31:0]       clk_counter;
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reg [2:0]        bit_counter;
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reg rx_buf;
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always @(posedge clk_i)
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        begin
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        if (rst_i) rx_buf <= 1'b1;
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        else rx_buf <= rx_i;
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        end
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always @(posedge clk_i)
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        begin
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        if (rst_i)
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                begin
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                state <= ST_NOSYNC;
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                clk_counter <= 32'h0;
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                bit_counter <= 3'h0;
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                locked_o <= 1'b0;
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                bitperiod_o <= 32'h0;
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                rx_done_tick_o <= 1'b0;
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                dout_bo <= 8'h0;
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                end
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        else
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                begin
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                rx_done_tick_o <= 1'b0;
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                case (state)
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                        ST_NOSYNC:
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                                begin
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                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_1;
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                                end
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                        ST_NOSYNC_WAIT1_1:
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                                begin
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                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_2;
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                                end
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                        ST_NOSYNC_WAIT0_2:
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                                begin
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                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_3;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT1_3:
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                                begin
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                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_4;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT0_4:
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                                begin
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                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_5;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT1_5:
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                                begin
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                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_6;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT0_6:
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                                begin
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                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_7;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT1_7:
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                                begin
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                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_8;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT0_8:
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                                begin
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                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT_STOP;
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_NOSYNC_WAIT_STOP:
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                                begin
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                                if (rx_buf == 1'b1)
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                                        begin
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                                        state <= ST_SYNC;
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                                        locked_o <= 1'b1;
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                                        bitperiod_o <= clk_counter[31:3];               // clk_counter / 8
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                                        dout_bo <= 32'h55;
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                                        rx_done_tick_o <= 1'b1;
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                                        end
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                                clk_counter <= clk_counter + 32'h1;
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                                end
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                        ST_SYNC:
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                                begin
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                                if (rx_buf == 1'b0)
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                                        begin
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                                        state <= ST_SYNC_WAIT_START;
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                                        clk_counter <= 32'h0;
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                                        end
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                                end
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                        ST_SYNC_WAIT_START:
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                                begin
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                                clk_counter <= clk_counter + 32'h1;
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                                if (clk_counter == {4'h0, bitperiod_o[28:1]})
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                                        begin
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                                        state <= ST_SYNC_RX_DATA;
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                                        clk_counter <= 32'h0;
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                                        bit_counter <= 3'h0;
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                                        end
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                                end
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                        ST_SYNC_RX_DATA:
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                                begin
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                                clk_counter <= clk_counter + 32'h1;
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                                if (clk_counter == {3'h0, bitperiod_o})
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                                        begin
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                                        dout_bo <= {rx_buf, dout_bo[7:1]};
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                                        clk_counter <= 32'h0;
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                                        bit_counter <= bit_counter + 3'h1;
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                                        if (bit_counter == 3'h7)
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                                                begin
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                                                rx_done_tick_o <= 1'b1;
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                                                state <= ST_SYNC_WAIT_STOP;
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                                                end
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                                        end
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                                end
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                        ST_SYNC_WAIT_STOP:
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                                begin
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                                if (rx_buf == 1'b1) state <= ST_SYNC;
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                                end
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                endcase
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                end
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        end
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endmodule

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