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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_sfr.v] - Blame information for rev 5

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module PSS_SFR
#(
        parameter CPU_RESET_DEFAULT = 1,
        parameter A31_DEFAULT = 1,
        parameter MEM_SIZE_KB = 1
)
(
        input clk_i, rst_i,
 
        // bus controls
        input bus_enb_i,
        input bus_we_i,
        input [31:0] bus_wdata_bi,
        input [31:0] bus_addr_bi,
        input [3:0] bus_writemask_bi,
        output reg bus_ack_o,
        output reg [31:0] bus_rdata_bo,
 
        // special function signals
        input cpu_present_i,
        input cpu_break_i,
        input [31:0] cpu_pc_bi,
 
        input trap_cpu_enb_i,
        input [31:0] trap_cpu_addr_bi,
 
        output reg cpu_reset_o,
        output cpu_enb_o,
        output reg a31_o,
 
        input bus_error_i,
        input [31:0] bus_error_addr_bi,
 
        // interrupts
        output reg bus_error_int_o,
        output reg sgi_int_o,
        output reg trap_int_o,
 
        // interrupt controller signals
        input intc_ie_i,
        input [7:0] intc_pending_bi,
        output reg intc_ie_we_o,
        output reg intc_ie_data_o,
        output reg [7:0] intc_mask_bo,
        output reg intc_clr_cmd_o,
        output reg [7:0] intc_clr_code_bo,
 
        // DMA controls
        output reg dma_req_o,
        output reg dma_cmd_o,
        output reg dma_autoinc_o,
        output reg [31:0] dma_size_bo,
        output reg [31:0] dma_sourceaddr_bo,
        output reg [31:0] dma_destaddr_bo
);
 
//// System registers ////
localparam REG_CPU_CONTROL_ADDR         = 8'h00;
localparam REG_CPU_PC_ADDR                      = 8'h04;
localparam REG_A31                                      = 8'h08;
 
localparam REG_INTC_CONTROL_ADDR        = 8'h10;
localparam REG_INTC_MASK_ADDR           = 8'h14;
localparam REG_INTC_REQ_ADDR            = 8'h18;
localparam REG_MEM_SIZE_KB                      = 8'h1C;
 
localparam REG_DMA_CONTROL_ADDR         = 8'h20;
localparam REG_DMA_SOURCEADDR_ADDR      = 8'h24;
localparam REG_DMA_DESTADDR_ADDR        = 8'h28;
localparam REG_DMA_SIZE_ADDR            = 8'h2C;
 
localparam REG_SGI_ADDR                         = 8'h30;
 
localparam REG_BUS_ERROR_ADDR_ADDR      = 8'h38;
localparam REG_BUS_ERROR_PC_ADDR        = 8'h3C;
 
localparam REG_TRAP_CONTROL_ADDR        = 8'h40;
localparam REG_TRAP_ADDR_ADDR           = 8'h44;
 
assign cpu_enb_o = 1'b1;
 
reg trap_enable;
reg [31:0] trap_addr;
 
reg [31:0] bus_error_pc;
reg [31:0] bus_error_addr;
 
reg bus_ack_rd;
always @(posedge clk_i)
        begin
        if (rst_i) bus_ack_rd <= 1'b0;
        else if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b0) && (bus_ack_rd == 1'b0)) bus_ack_rd <= 1'b1;
        else bus_ack_rd <= 1'b0;
        end
 
always @*
        begin
        if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b1)) bus_ack_o = 1'b1;
        else bus_ack_o = bus_ack_rd;
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
 
                cpu_reset_o <= CPU_RESET_DEFAULT;
                a31_o <= A31_DEFAULT;
 
                trap_enable <= 1'b0;
                trap_addr <= 32'h0;
 
                sgi_int_o <= 1'b0;
 
                dma_req_o <= 1'b0;
                dma_cmd_o <= 1'b0;
                dma_autoinc_o <= 1'b0;
 
                intc_ie_we_o <= 1'b0;
                intc_ie_data_o <= 1'bx;
                intc_mask_bo <= 8'h0;
                intc_clr_cmd_o <= 1'b0;
                intc_clr_code_bo <= 8'hx;
 
                dma_sourceaddr_bo <= 32'h0;
                dma_destaddr_bo <= 32'h0;
                dma_size_bo <= 32'h0;
                end
        else
                begin
 
                sgi_int_o <= 1'b0;
 
                intc_ie_we_o <= 1'b0;
                intc_clr_cmd_o <= 1'b0;
                bus_rdata_bo <= 32'hx;
 
                dma_req_o <= 1'b0;
 
                if (bus_enb_i == 1'b1)
                        begin
                        if (bus_we_i == 1'b0)
                                case (bus_addr_bi[7:0])
                                        REG_CPU_CONTROL_ADDR:           bus_rdata_bo <= {cpu_present_i, 29'h0, cpu_break_i, cpu_reset_o};
                                        REG_CPU_PC_ADDR:                        bus_rdata_bo <= cpu_pc_bi;
                                        REG_A31:                                        bus_rdata_bo <= {31'h0, a31_o};
 
                                        REG_INTC_CONTROL_ADDR:          bus_rdata_bo <= {31'h0, intc_ie_i};
                                        REG_INTC_MASK_ADDR:                     bus_rdata_bo <= {24'h0, intc_mask_bo};
                                        REG_INTC_REQ_ADDR:                      bus_rdata_bo <= {24'h0, intc_pending_bi};
                                        REG_MEM_SIZE_KB:                        bus_rdata_bo <= MEM_SIZE_KB;
 
                                        REG_DMA_SOURCEADDR_ADDR:        bus_rdata_bo <= dma_sourceaddr_bo;
                                        REG_DMA_DESTADDR_ADDR:          bus_rdata_bo <= dma_destaddr_bo;
                                        REG_DMA_SIZE_ADDR:                      bus_rdata_bo <= dma_size_bo;
 
                                        REG_TRAP_CONTROL_ADDR:          bus_rdata_bo <= {31'h0, trap_enable};
                                        REG_TRAP_ADDR_ADDR:                     bus_rdata_bo <= trap_addr;
 
                                        REG_BUS_ERROR_ADDR_ADDR:        bus_rdata_bo <= bus_error_addr;
                                        REG_BUS_ERROR_PC_ADDR:          bus_rdata_bo <= bus_error_pc;
                                endcase
                        else
                                case (bus_addr_bi[7:0])
                                        REG_CPU_CONTROL_ADDR:           cpu_reset_o <= bus_wdata_bi[0];
                                        REG_A31:                                        a31_o <= bus_wdata_bi[0];
 
                                        REG_INTC_CONTROL_ADDR:          begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
                                        REG_INTC_MASK_ADDR:                     intc_mask_bo <= bus_wdata_bi[7:0];
                                        REG_INTC_REQ_ADDR:                      begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
 
                                        REG_DMA_CONTROL_ADDR:           begin dma_req_o <= 1'b1; dma_cmd_o <= bus_wdata_bi[1]; dma_autoinc_o <= bus_wdata_bi[2]; end
                                        REG_DMA_SOURCEADDR_ADDR:        begin
                                                                                                        if (bus_wdata_bi[31] == 1'b1)
                                                                                                                dma_sourceaddr_bo <= {a31_o, bus_wdata_bi[30:0]};
                                                                                                        else
                                                                                                                dma_sourceaddr_bo <= bus_wdata_bi;
                                                                                                end
                                        REG_DMA_DESTADDR_ADDR:          begin
 
                                                                                                        if (bus_wdata_bi[31] == 1'b1)
                                                                                                                dma_destaddr_bo <= {a31_o, bus_wdata_bi[30:0]};
                                                                                                        else
                                                                                                                dma_destaddr_bo <= bus_wdata_bi;
                                                                                                end
                                        REG_DMA_SIZE_ADDR:                      dma_size_bo <= bus_wdata_bi;
 
                                        REG_SGI_ADDR:                           sgi_int_o <= 1'b1;
 
                                        REG_TRAP_CONTROL_ADDR:          trap_enable <= bus_wdata_bi[0];
                                        REG_TRAP_ADDR_ADDR:                     trap_addr <= bus_wdata_bi;
                                endcase
                        end
                end
        end
 
// trap logic
always @(posedge clk_i)
        begin
        if (rst_i)
                trap_int_o <= 1'b0;
        else
                begin
                trap_int_o <= 1'b0;
                if (trap_enable == 1'b1)
                        if (trap_cpu_enb_i == 1'b1)
                                if (trap_cpu_addr_bi == trap_addr)
                                        trap_int_o <= 1'b1;
                end
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                bus_error_int_o <= 1'b0;
                bus_error_addr <= 32'h0;
                bus_error_pc <= 32'h0;
                end
        else
                begin
                bus_error_int_o <= 1'b0;
                if (bus_error_i == 1'b1)
                        begin
                        bus_error_int_o <= 1'b1;
                        bus_error_addr <= bus_error_addr_bi;
                        bus_error_pc <= cpu_pc_bi;
                        end
                end
        end
 
endmodule

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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_sfr.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	AlexAntono	`module PSS_SFR`
2			`#(`
3			`parameter CPU_RESET_DEFAULT = 1,`
4			`parameter A31_DEFAULT = 1,`
5			`parameter MEM_SIZE_KB = 1`
6			`)`
7			`(`
8			`input clk_i, rst_i,`
9
10			`// bus controls`
11			`input bus_enb_i,`
12			`input bus_we_i,`
13			`input [31:0] bus_wdata_bi,`
14			`input [31:0] bus_addr_bi,`
15			`input [3:0] bus_writemask_bi,`
16			`output reg bus_ack_o,`
17			`output reg [31:0] bus_rdata_bo,`
18
19			`// special function signals`
20			`input cpu_present_i,`
21			`input cpu_break_i,`
22			`input [31:0] cpu_pc_bi,`
23
24			`input trap_cpu_enb_i,`
25			`input [31:0] trap_cpu_addr_bi,`
26
27			`output reg cpu_reset_o,`
28			`output cpu_enb_o,`
29			`output reg a31_o,`
30
31			`input bus_error_i,`
32			`input [31:0] bus_error_addr_bi,`
33
34			`// interrupts`
35			`output reg bus_error_int_o,`
36			`output reg sgi_int_o,`
37			`output reg trap_int_o,`
38
39			`// interrupt controller signals`
40			`input intc_ie_i,`
41			`input [7:0] intc_pending_bi,`
42			`output reg intc_ie_we_o,`
43			`output reg intc_ie_data_o,`
44			`output reg [7:0] intc_mask_bo,`
45			`output reg intc_clr_cmd_o,`
46			`output reg [7:0] intc_clr_code_bo,`
47
48			`// DMA controls`
49			`output reg dma_req_o,`
50			`output reg dma_cmd_o,`
51			`output reg dma_autoinc_o,`
52			`output reg [31:0] dma_size_bo,`
53			`output reg [31:0] dma_sourceaddr_bo,`
54			`output reg [31:0] dma_destaddr_bo`
55			`);`
56
57			`//// System registers ////`
58			`localparam REG_CPU_CONTROL_ADDR = 8'h00;`
59			`localparam REG_CPU_PC_ADDR = 8'h04;`
60			`localparam REG_A31 = 8'h08;`
61
62			`localparam REG_INTC_CONTROL_ADDR = 8'h10;`
63			`localparam REG_INTC_MASK_ADDR = 8'h14;`
64			`localparam REG_INTC_REQ_ADDR = 8'h18;`
65			`localparam REG_MEM_SIZE_KB = 8'h1C;`
66
67			`localparam REG_DMA_CONTROL_ADDR = 8'h20;`
68			`localparam REG_DMA_SOURCEADDR_ADDR = 8'h24;`
69			`localparam REG_DMA_DESTADDR_ADDR = 8'h28;`
70			`localparam REG_DMA_SIZE_ADDR = 8'h2C;`
71
72			`localparam REG_SGI_ADDR = 8'h30;`
73
74			`localparam REG_BUS_ERROR_ADDR_ADDR = 8'h38;`
75			`localparam REG_BUS_ERROR_PC_ADDR = 8'h3C;`
76
77			`localparam REG_TRAP_CONTROL_ADDR = 8'h40;`
78			`localparam REG_TRAP_ADDR_ADDR = 8'h44;`
79
80			`assign cpu_enb_o = 1'b1;`
81
82			`reg trap_enable;`
83			`reg [31:0] trap_addr;`
84
85			`reg [31:0] bus_error_pc;`
86			`reg [31:0] bus_error_addr;`
87
88			`reg bus_ack_rd;`
89			`always @(posedge clk_i)`
90			`begin`
91			`if (rst_i) bus_ack_rd <= 1'b0;`
92			`else if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b0) && (bus_ack_rd == 1'b0)) bus_ack_rd <= 1'b1;`
93			`else bus_ack_rd <= 1'b0;`
94			`end`
95
96			`always @*`
97			`begin`
98			`if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b1)) bus_ack_o = 1'b1;`
99			`else bus_ack_o = bus_ack_rd;`
100			`end`
101
102			`always @(posedge clk_i)`
103			`begin`
104			`if (rst_i)`
105			`begin`
106
107			`cpu_reset_o <= CPU_RESET_DEFAULT;`
108			`a31_o <= A31_DEFAULT;`
109
110			`trap_enable <= 1'b0;`
111			`trap_addr <= 32'h0;`
112
113			`sgi_int_o <= 1'b0;`
114
115			`dma_req_o <= 1'b0;`
116			`dma_cmd_o <= 1'b0;`
117			`dma_autoinc_o <= 1'b0;`
118
119			`intc_ie_we_o <= 1'b0;`
120			`intc_ie_data_o <= 1'bx;`
121			`intc_mask_bo <= 8'h0;`
122			`intc_clr_cmd_o <= 1'b0;`
123			`intc_clr_code_bo <= 8'hx;`
124
125			`dma_sourceaddr_bo <= 32'h0;`
126			`dma_destaddr_bo <= 32'h0;`
127			`dma_size_bo <= 32'h0;`
128			`end`
129			`else`
130			`begin`
131
132			`sgi_int_o <= 1'b0;`
133
134			`intc_ie_we_o <= 1'b0;`
135			`intc_clr_cmd_o <= 1'b0;`
136			`bus_rdata_bo <= 32'hx;`
137
138			`dma_req_o <= 1'b0;`
139
140			`if (bus_enb_i == 1'b1)`
141			`begin`
142			`if (bus_we_i == 1'b0)`
143			`case (bus_addr_bi[7:0])`
144			`REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 29'h0, cpu_break_i, cpu_reset_o};`
145			`REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;`
146			`REG_A31: bus_rdata_bo <= {31'h0, a31_o};`
147
148			`REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};`
149			`REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};`
150			`REG_INTC_REQ_ADDR: bus_rdata_bo <= {24'h0, intc_pending_bi};`
151			`REG_MEM_SIZE_KB: bus_rdata_bo <= MEM_SIZE_KB;`
152
153			`REG_DMA_SOURCEADDR_ADDR: bus_rdata_bo <= dma_sourceaddr_bo;`
154			`REG_DMA_DESTADDR_ADDR: bus_rdata_bo <= dma_destaddr_bo;`
155			`REG_DMA_SIZE_ADDR: bus_rdata_bo <= dma_size_bo;`
156
157			`REG_TRAP_CONTROL_ADDR: bus_rdata_bo <= {31'h0, trap_enable};`
158			`REG_TRAP_ADDR_ADDR: bus_rdata_bo <= trap_addr;`
159
160			`REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;`
161			`REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;`
162			`endcase`
163			`else`
164			`case (bus_addr_bi[7:0])`
165			`REG_CPU_CONTROL_ADDR: cpu_reset_o <= bus_wdata_bi[0];`
166			`REG_A31: a31_o <= bus_wdata_bi[0];`
167
168			`REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end`
169			`REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];`
170			`REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end`
171
172			`REG_DMA_CONTROL_ADDR: begin dma_req_o <= 1'b1; dma_cmd_o <= bus_wdata_bi[1]; dma_autoinc_o <= bus_wdata_bi[2]; end`
173			`REG_DMA_SOURCEADDR_ADDR: begin`
174			`if (bus_wdata_bi[31] == 1'b1)`
175			`dma_sourceaddr_bo <= {a31_o, bus_wdata_bi[30:0]};`
176			`else`
177			`dma_sourceaddr_bo <= bus_wdata_bi;`
178			`end`
179			`REG_DMA_DESTADDR_ADDR: begin`
180
181			`if (bus_wdata_bi[31] == 1'b1)`
182			`dma_destaddr_bo <= {a31_o, bus_wdata_bi[30:0]};`
183			`else`
184			`dma_destaddr_bo <= bus_wdata_bi;`
185			`end`
186			`REG_DMA_SIZE_ADDR: dma_size_bo <= bus_wdata_bi;`
187
188			`REG_SGI_ADDR: sgi_int_o <= 1'b1;`
189
190			`REG_TRAP_CONTROL_ADDR: trap_enable <= bus_wdata_bi[0];`
191			`REG_TRAP_ADDR_ADDR: trap_addr <= bus_wdata_bi;`
192			`endcase`
193			`end`
194			`end`
195			`end`
196
197			`// trap logic`
198			`always @(posedge clk_i)`
199			`begin`
200			`if (rst_i)`
201			`trap_int_o <= 1'b0;`
202			`else`
203			`begin`
204			`trap_int_o <= 1'b0;`
205			`if (trap_enable == 1'b1)`
206			`if (trap_cpu_enb_i == 1'b1)`
207			`if (trap_cpu_addr_bi == trap_addr)`
208			`trap_int_o <= 1'b1;`
209			`end`
210			`end`
211
212			`always @(posedge clk_i)`
213			`begin`
214			`if (rst_i)`
215			`begin`
216			`bus_error_int_o <= 1'b0;`
217			`bus_error_addr <= 32'h0;`
218			`bus_error_pc <= 32'h0;`
219			`end`
220			`else`
221			`begin`
222			`bus_error_int_o <= 1'b0;`
223			`if (bus_error_i == 1'b1)`
224			`begin`
225			`bus_error_int_o <= 1'b1;`
226			`bus_error_addr <= bus_error_addr_bi;`
227			`bus_error_pc <= cpu_pc_bi;`
228			`end`
229			`end`
230			`end`
231
232			`endmodule`