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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company: KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author: P.J.J. Lemmens
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-- Design Name: Feature Extraction
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-- Module Name: CF_process.vhd
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-- Description: - baseline sampling, calculation & correction
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-- - Constant Fraction pulse construction
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-- - Zero-crossing detection
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-- - event-detection
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-- - baseline_sampling & event_detection gating/inhibition
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-- - sub_sample timing calculation through interpolation
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-- - time-stamp generation
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-- - energy reading/peak-detection
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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use IEEE.numeric_std.ALL;
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entity CF_process is
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generic( WIDTH : natural := 1;
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MAX_CF_PWR : natural := 1;-- CF_DELAY : natural := 1;-- CF_PWR : natural := 1;
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MAX_BASELINE_PWR : natural := 1;
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ZEROX_WINDOW_PWR : natural := 1;
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ZEROX_THRESHOLD_PWR : natural := 1;-- INTEGRAL_PWR : natural := 1;-- INTEGRAL_THRESHOLD_PWR : natural := 1;
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INTERP_CYCLES : natural := 1
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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baseline_enable : in STD_LOGIC;
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double_CF_in : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
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threshold_in : in STD_LOGIC_VECTOR;
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cf_pwr_in : in STD_LOGIC_VECTOR;
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cf_integral_pwr_in : in STD_LOGIC_VECTOR;
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baseline_pwr_in : in STD_LOGIC_VECTOR;
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baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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event_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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baseline_out : out STD_LOGIC_VECTOR;
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clamped_out : out STD_LOGIC_VECTOR;
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del_clamp_out : out STD_LOGIC_VECTOR;
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CFdev_clamp_out : out STD_LOGIC_VECTOR;
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cf_trace_out : out STD_LOGIC_VECTOR;
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integral : out STD_LOGIC_VECTOR;
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sample_nr : out STD_LOGIC_VECTOR;
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zeroX_out : out STD_LOGIC;
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event_detect_out : out STD_LOGIC;
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bl_gate_out : out STD_LOGIC;
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ed_gate_out : out STD_LOGIC;
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eventdata_valid : out STD_LOGIC;
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eventnr_out : out STD_LOGIC_VECTOR;
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fraction : out STD_LOGIC_VECTOR;
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energy : out STD_LOGIC_VECTOR
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);
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end CF_process;
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architecture Behavioral of CF_process is
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constant MAX_CF_DELAY : natural := 2**MAX_CF_PWR;
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constant PEAK_DET_BUF_PWR : natural := 4;
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constant PEAK_DET_BUFSIZE : natural := 2**PEAK_DET_BUF_PWR;
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-- constant CFWINDOW_SIZE : natural := 2**CF_WINDOW_PWR;
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-- constant INTEGRAL_SIZE : natural := 2**INTEGRAL_PWR;
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constant FRACTION_SIZE : natural := INTERP_CYCLES; -- - ZEROX_WINDOW_PWR; --all interp bits are fraction now !! interp between 2 samples
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-- constant GATE_PWR : natural := BASELINE_PWR;
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component baseline_follower
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generic( WINDOW_PWR : natural := 1; -- defines the maximum window in which event disturbance is seen
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MAX_BASELINE_PWR : natural := 1 -- size of the baseline window
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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gate : in STD_LOGIC;
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baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0);
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buffer_size_in : in STD_LOGIC_VECTOR(7 downto 0);
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data_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR;
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buffer_data_valid : out STD_LOGIC
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);
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end component;
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component SISO_sub_a
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generic( A_MINUS_B : boolean);
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port (
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dataa : IN STD_LOGIC_VECTOR;
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datab : IN STD_LOGIC_VECTOR;
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result : OUT STD_LOGIC_VECTOR
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);
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end component;
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component progdelay_pipeline
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generic (RAM_SIZE_PWR : natural := 1;
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FLEX_RAM_STYLE : string := "distributed");
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Port (clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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delay_in : in STD_LOGIC_VECTOR(7 downto 0);
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data_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR;
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data_valid : out std_logic
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);
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end component;
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component CF_zeroX
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generic( BASE_WINDOW_PWR : natural;
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ZEROX_WINDOW_PWR : natural;
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ZEROX_THRESHOLD_PWR : natural
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);
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port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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zeroX_out : out STD_LOGIC
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);
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end component;
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component moving_average_programmable
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generic(MEM_PWR : natural);
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port (rst : in std_logic;
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clk : in std_logic;
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enable : in std_logic;
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program : in std_logic;
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avg_pwr_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector;
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data_out : out std_logic_vector
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);
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end component;
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component gate_generator
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-- generic( BASE_WINDOW_PWR : natural := 1;
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-- EVENT_INHIB_PWR : natural := 1
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-- );
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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baseline_enable : in STD_LOGIC;
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event_in : in STD_LOGIC;
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baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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event_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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bl_gate_out : out STD_LOGIC; -- baseline gate-signal
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ed_gate_out : out STD_LOGIC -- baseline gating inhibited because of event
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);
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end component;
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component timing_linear_interp
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generic( INTERP_CYCLES : natural);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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trigger : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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samplenr_in : in STD_LOGIC_VECTOR;
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eventnr_out : out STD_LOGIC_VECTOR;
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fraction_out : out STD_LOGIC_VECTOR;
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eventdata_valid : out STD_LOGIC
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);
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end component;
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component sample_counter
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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sample_nr_out : out STD_LOGIC_VECTOR (63 downto 0)
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);
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end component;
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component history_max
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generic( MEM_PWR : natural := 1;
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DEPTH : natural := 1
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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trigger : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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max_valid : out STD_LOGIC;
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max_out : out STD_LOGIC_VECTOR
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);
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end component;
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component event_detector
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Port ( clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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gate_in : in STD_LOGIC;
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zeroX_in : in STD_LOGIC;
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threshold_in : in STD_LOGIC_VECTOR;
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integral_in : in STD_LOGIC_VECTOR;
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event_detect_out : out STD_LOGIC
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);
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end component;
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-----------------------------------------------------------------------
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal program_S : std_logic := '0';
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signal baseline_enable_S : STD_LOGIC := '0';
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signal double_CF_S : STD_LOGIC := '0';
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signal data_in_S : std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
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signal baseline_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal clamped_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal CFdev_clamp_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal del_clamp_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal cf_trace_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal threshold_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal integral_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal cf_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value
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signal cf_integral_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value = (mwd_power - 1)
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signal cf_delay_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(16, 8);
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signal baseline_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal baseline_delay_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal baseline_inhibit_cnt_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(32, 8); -- original default value
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signal event_inhibit_cnt_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(16, 8); -- original default value
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signal event_detect_S : std_logic := '0';
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signal zeroX_S : STD_LOGIC := '0';
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signal bl_gate_S : STD_LOGIC := '0';
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signal ed_gate_S : STD_LOGIC := '0';
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signal sample_nr_S : STD_LOGIC_VECTOR (63 downto 0) := (others => '0');
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signal eventnr_S : STD_LOGIC_VECTOR (63 downto 0) := (others => '0');
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signal time_fraction_S : STD_LOGIC_VECTOR (FRACTION_SIZE - 1 downto 0) := (others => '0');
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signal energy_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');
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signal eventdata_valid_S : STD_LOGIC := '0';
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signal max_valid_S : STD_LOGIC := '0';
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-----------------------------------------------------------------------
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begin
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baseline : baseline_follower
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generic map(WINDOW_PWR => MAX_CF_PWR,
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MAX_BASELINE_PWR => MAX_BASELINE_PWR
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)
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port map ( rst => rst_S,
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clk => clk_S,
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enable => enable_S,
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program => program_S,
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gate => bl_gate_S,
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baseline_pwr_in => baseline_pwr_S,
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buffer_size_in => baseline_delay_S,
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data_in => data_in_S,
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data_out => baseline_S,
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buffer_data_valid => open
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);
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remove_baseline : SISO_sub_a
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GENERIC MAP(--WIDTH => data_in_S'length,
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A_MINUS_B => true)
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PORT MAP ( dataa => data_in_S,
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datab => baseline_S,
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result => clamped_S
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);
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clamped_pipe : progdelay_pipeline
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generic map(RAM_SIZE_PWR => MAX_CF_PWR,
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FLEX_RAM_STYLE => "distributed")
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PORT MAP(rst => rst_S,
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clk => clk_S,
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enable => enable_S,
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program => program_S,
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delay_in => cf_delay_S,
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data_in => clamped_S,
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data_out => del_clamp_S,
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data_valid => open
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);
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CF_sub : SISO_sub_a
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GENERIC MAP(--WIDTH => cf_trace_S'length,
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A_MINUS_B => true)
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PORT MAP ( dataa => del_clamp_S,
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datab => CFdev_clamp_S,
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result => cf_trace_S
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);
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zeroX : CF_zeroX
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generic map(BASE_WINDOW_PWR => MAX_CF_PWR, -- CF_WINDOW_PWR,
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ZEROX_WINDOW_PWR => ZEROX_WINDOW_PWR,
|
314 |
|
|
ZEROX_THRESHOLD_PWR => ZEROX_THRESHOLD_PWR
|
315 |
|
|
)
|
316 |
|
|
port map ( rst => rst_S,
|
317 |
|
|
clk => clk_S,
|
318 |
|
|
enable => enable_S,
|
319 |
|
|
data_in => cf_trace_S,
|
320 |
|
|
zeroX_out => zeroX_S
|
321 |
|
|
);
|
322 |
|
|
|
323 |
|
|
CF_integral : moving_average_programmable
|
324 |
|
|
generic map(MEM_PWR => MAX_CF_PWR)
|
325 |
|
|
port map( rst => rst_S,
|
326 |
|
|
clk => clk_S,
|
327 |
|
|
enable => enable_S,
|
328 |
|
|
program => program_S,
|
329 |
|
|
avg_pwr_in => cf_integral_pwr_S,
|
330 |
|
|
data_in => clamped_S,
|
331 |
|
|
data_out => integral_S
|
332 |
|
|
);
|
333 |
|
|
|
334 |
|
|
gator : gate_generator
|
335 |
|
|
-- generic map(BASE_WINDOW_PWR => GATE_PWR,
|
336 |
|
|
-- EVENT_INHIB_PWR => MAX_CF_PWR --CF_WINDOW_PWR
|
337 |
|
|
-- )
|
338 |
|
|
port map ( rst => rst_S,
|
339 |
|
|
clk => clk_S,
|
340 |
|
|
enable => enable_S,
|
341 |
|
|
program => program_S,
|
342 |
|
|
baseline_enable => baseline_enable_S,
|
343 |
|
|
event_in => event_detect_S,
|
344 |
|
|
baseline_inhibit_cnt_in => baseline_inhibit_cnt_S,
|
345 |
|
|
event_inhibit_cnt_in => event_inhibit_cnt_S,
|
346 |
|
|
bl_gate_out => bl_gate_S,
|
347 |
|
|
ed_gate_out => ed_gate_S
|
348 |
|
|
);
|
349 |
|
|
|
350 |
|
|
timing : timing_linear_interp
|
351 |
|
|
generic map(INTERP_CYCLES => INTERP_CYCLES)
|
352 |
|
|
Port map( rst => rst_S,
|
353 |
|
|
clk => clk_S,
|
354 |
|
|
enable => enable_S,
|
355 |
|
|
trigger => event_detect_S,
|
356 |
|
|
data_in => cf_trace_S,
|
357 |
|
|
samplenr_in => sample_nr_S,
|
358 |
|
|
eventnr_out => eventnr_S,
|
359 |
|
|
fraction_out => time_fraction_S,
|
360 |
|
|
eventdata_valid => eventdata_valid_S
|
361 |
|
|
);
|
362 |
|
|
|
363 |
|
|
time_stamp : sample_counter
|
364 |
|
|
Port map( rst => rst_S,
|
365 |
|
|
clk => clk_S,
|
366 |
|
|
enable => enable_S,
|
367 |
|
|
sample_nr_out => sample_nr_S
|
368 |
|
|
);
|
369 |
|
|
|
370 |
|
|
peak_detect : history_max
|
371 |
|
|
generic map(MEM_PWR => PEAK_DET_BUF_PWR, --CF_WINDOW_PWR,
|
372 |
|
|
DEPTH => PEAK_DET_BUFSIZE) --CF_WINDOWSIZE -10
|
373 |
|
|
port map ( rst => rst_S,
|
374 |
|
|
clk => clk_S,
|
375 |
|
|
enable => enable_S,
|
376 |
|
|
trigger => event_detect_S,
|
377 |
|
|
data_in => clamped_S,
|
378 |
|
|
max_valid => max_valid_S,
|
379 |
|
|
max_out => energy_S
|
380 |
|
|
);
|
381 |
|
|
|
382 |
|
|
eventdetect : event_detector
|
383 |
|
|
Port map( clk => clk_S,
|
384 |
|
|
enable => enable_S,
|
385 |
|
|
gate_in => ed_gate_S,
|
386 |
|
|
zeroX_in => zeroX_S,
|
387 |
|
|
threshold_in => threshold_S,
|
388 |
|
|
integral_in => integral_S,
|
389 |
|
|
event_detect_out => event_detect_S
|
390 |
|
|
);
|
391 |
|
|
|
392 |
|
|
rst_S <= rst;
|
393 |
|
|
clk_S <= clk;
|
394 |
|
|
enable_S <= enable;
|
395 |
|
|
program_S <= program;
|
396 |
|
|
baseline_enable_S <= baseline_enable;
|
397 |
|
|
double_CF_S <= double_CF_in;
|
398 |
|
|
data_in_S <= data_in; -- add a sign bit to avoid disaster
|
399 |
|
|
cf_pwr_S <= cf_pwr_in;
|
400 |
|
|
cf_delay_S <= conv_std_logic_vector((2**conv_integer(cf_pwr_S)), 8);
|
401 |
|
|
baseline_delay_S <= conv_std_logic_vector((2**(conv_integer(cf_pwr_S)) + 16), 8);
|
402 |
|
|
cf_integral_pwr_S <= cf_integral_pwr_in;
|
403 |
|
|
baseline_pwr_S <= baseline_pwr_in;
|
404 |
|
|
baseline_inhibit_cnt_S <= baseline_inhibit_cnt_in;
|
405 |
|
|
event_inhibit_cnt_S <= event_inhibit_cnt_in;
|
406 |
|
|
baseline_out <= baseline_S;
|
407 |
|
|
clamped_out <= clamped_S;
|
408 |
|
|
|
409 |
|
|
CF_mux : process(double_CF_S, clamped_S)
|
410 |
|
|
begin
|
411 |
|
|
case (double_CF_S) is
|
412 |
|
|
when '1' =>
|
413 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);
|
414 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);
|
415 |
|
|
CFdev_clamp_S((CFdev_clamp_S'high - 2) downto 0) <= clamped_S((clamped_S'high - 1) downto 1);
|
416 |
|
|
when '0' =>
|
417 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);
|
418 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);
|
419 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high - 2) <= clamped_S(clamped_S'high);
|
420 |
|
|
CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);
|
421 |
|
|
when others =>
|
422 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);
|
423 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);
|
424 |
|
|
CFdev_clamp_S(CFdev_clamp_S'high - 2) <= clamped_S(clamped_S'high);
|
425 |
|
|
CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);
|
426 |
|
|
end case;
|
427 |
|
|
end process;
|
428 |
|
|
|
429 |
|
|
del_clamp_out <= del_clamp_S;
|
430 |
|
|
CFdev_clamp_out <= CFdev_clamp_S;
|
431 |
|
|
cf_trace_out <= cf_trace_S;
|
432 |
|
|
threshold_S <= threshold_in;
|
433 |
|
|
integral <= integral_S;
|
434 |
|
|
sample_nr <= sample_nr_S;
|
435 |
|
|
zeroX_out <= zeroX_S;
|
436 |
|
|
event_detect_out <= event_detect_S;
|
437 |
|
|
bl_gate_out <= bl_gate_S;
|
438 |
|
|
ed_gate_out <= ed_gate_S;
|
439 |
|
|
eventdata_valid <= eventdata_valid_S;
|
440 |
|
|
eventnr_out <= eventnr_S;
|
441 |
|
|
fraction <= time_fraction_S;
|
442 |
|
|
energy <= energy_S;
|
443 |
|
|
|
444 |
|
|
end Behavioral;
|