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panda_emc |
-----------------------------------------------------------------------------------------------
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company: KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author: P.J.J. Lemmens
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-- Design Name: Feature Extraction
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-- Module Name: MWD_CF_process.vhd
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-- Description: - Moving Window Deconvolution ("MWD_programmable")
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-- - Pulse Reshape module ("shaper")
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-- - switch/multiplexer ("mux_sre")
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-- - Constant Fraction pulse-detection ("CF_process")
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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entity MWD_CF_process is
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generic( WIDTH : natural := 1;
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MAX_MWD_PWR : natural := 1;
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MAX_CF_PWR : natural := 1;
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MAX_BASELINE_PWR : natural := 1;
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ZEROX_WINDOW_PWR : natural := 1;
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ZEROX_THRESHOLD_PWR : natural := 1;
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INTERP_CYCLES : natural := 1
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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baseline_enable : in STD_LOGIC;
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double_CF_in : in STD_LOGIC;
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bypass_mwd : in STD_LOGIC;
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bypass_reshape : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
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invert_data_in : in STD_LOGIC;
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decay_correction_in : in STD_LOGIC_VECTOR;
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reshape_correction_in : in STD_LOGIC_VECTOR;
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threshold_in : in STD_LOGIC_VECTOR;
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mwd_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for mwd-windowsize
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cf_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for cf-delay
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cf_integral_pwr_in : in std_logic_vector(7 downto 0); -- power of 2 for CF integral
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baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0);
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baseline_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- baseline data-collect inhibition after event
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event_inhibit_cnt_in : in std_logic_vector(7 downto 0); -- event detect inhibition after event
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mwd_switch_out : out STD_LOGIC_VECTOR;
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baseline_out : out STD_LOGIC_VECTOR;
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clamped_out : out STD_LOGIC_VECTOR;
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del_clamp_out : out STD_LOGIC_VECTOR;
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CFdev_clamp_out : out STD_LOGIC_VECTOR;
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cf_trace_out : out STD_LOGIC_VECTOR;
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integral : out STD_LOGIC_VECTOR;
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sample_nr : out STD_LOGIC_VECTOR;
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zeroX_out : out STD_LOGIC;
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event_detect_out : out STD_LOGIC;
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bl_gate_out : out STD_LOGIC;
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ed_gate_out : out STD_LOGIC;
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eventdata_valid : out STD_LOGIC;
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eventnr_out : out STD_LOGIC_VECTOR;
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fraction : out STD_LOGIC_VECTOR;
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energy : out STD_LOGIC_VECTOR
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);
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end MWD_CF_process;
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architecture Behavioral of MWD_CF_process is
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constant SIGNED_WIDTH : natural := WIDTH + 1;
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constant FRACTION_SIZE : natural := INTERP_CYCLES;-- - ZEROX_WINDOW_PWR; --all interp bits are fraction now !! interp between 2 samples
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constant MAX_RESHAPE_PWR : natural := 2;
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component MWD_programmable
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generic( MAX_MWD_PWR : natural);
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in std_logic;
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mwd_pwr_in : in std_logic_vector(7 downto 0);
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data_in : in STD_LOGIC_VECTOR;
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correction_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR
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);
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end component;
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component shaper
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in std_logic;
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data_in : in STD_LOGIC_VECTOR;
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correction_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR
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);
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end component;
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component mux_sre
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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selectB : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR;
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b : in STD_LOGIC_VECTOR;
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data_valid : out STD_LOGIC;
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q : out STD_LOGIC_VECTOR
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);
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end component;
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COMPONENT CF_process
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generic( WIDTH : natural := 1;
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MAX_CF_PWR : natural := 1;
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MAX_BASELINE_PWR : natural := 1;
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ZEROX_WINDOW_PWR : natural := 1;
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ZEROX_THRESHOLD_PWR : natural := 1;-- INTEGRAL_PWR : natural := 1;
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INTERP_CYCLES : natural := 1
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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baseline_enable : in STD_LOGIC;
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double_CF_in : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
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threshold_in : in STD_LOGIC_VECTOR;
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cf_pwr_in : in STD_LOGIC_VECTOR;
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cf_integral_pwr_in : in STD_LOGIC_VECTOR;
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baseline_pwr_in : in STD_LOGIC_VECTOR;
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baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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event_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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baseline_out : out STD_LOGIC_VECTOR;
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clamped_out : out STD_LOGIC_VECTOR;
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del_clamp_out : out STD_LOGIC_VECTOR;
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CFdev_clamp_out : out STD_LOGIC_VECTOR;
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cf_trace_out : out STD_LOGIC_VECTOR;
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integral : out STD_LOGIC_VECTOR;
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sample_nr : out STD_LOGIC_VECTOR;
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zeroX_out : out STD_LOGIC;
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event_detect_out : out STD_LOGIC;
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bl_gate_out : out STD_LOGIC;
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ed_gate_out : out STD_LOGIC;
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eventdata_valid : out STD_LOGIC;
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eventnr_out : out STD_LOGIC_VECTOR;
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fraction : out STD_LOGIC_VECTOR;
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energy : out STD_LOGIC_VECTOR
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);
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END COMPONENT;
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-----------------------------------------------------------------------
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal program_S : std_logic := '0';
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signal baseline_enable_S : std_logic := '0';
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signal double_CF_S : std_logic := '0';
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signal bypass_mwd_S : std_logic := '0';
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signal bypass_reshape_S : std_logic := '0';
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signal udata_in_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal invert_data_in_S : std_logic := '0';
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signal data_in_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal decay_correction_S : std_logic_vector(decay_correction_in'high downto 0) := (others => '0');
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signal reshape_correction_S : std_logic_vector(reshape_correction_in'high downto 0) := (others => '0');
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signal threshold_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal mwd_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(5, 8); -- original default value
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signal cf_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(4, 8); -- original default value
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signal cf_integral_pwr_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(4, 8); -- original default value = (mwd_power - 1)
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signal baseline_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
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signal baseline_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value
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signal event_inhibit_cnt_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(16, 8); -- original default value
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signal short_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal reshaped_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal mwd_switch_out_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal mwd_switch_data_valid_S : std_logic := '0';
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signal reshape_switch_out_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal reshape_switch_data_valid_S : std_logic := '0';
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signal baseline_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal clamped_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal CFdev_clamp_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal del_clamp_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal cf_trace_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal integral_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal event_detect_S : std_logic := '0';
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signal zeroX_S : STD_LOGIC := '0';
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signal bl_gate_S : STD_LOGIC := '0';
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signal ed_gate_S : STD_LOGIC := '0';
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signal sample_nr_S : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
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signal eventnr_S : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
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signal fraction_S : STD_LOGIC_VECTOR(FRACTION_SIZE - 1 downto 0) := (others => '0');
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signal energy_S : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
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signal eventdata_valid_S : STD_LOGIC := '0';
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-----------------------------------------------------------------------
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begin
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mwd : MWD_programmable
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generic map(MAX_MWD_PWR => MAX_MWD_PWR)
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port map(rst => rst_S,
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clk => clk_S,
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enable => enable_S,
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program => program_S,
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mwd_pwr_in => mwd_pwr_S,
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data_in => data_in_S,
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correction_in => decay_correction_S,
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data_out => short_S
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);
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mwd_switch : mux_sre
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port map(rst => rst_S,
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clk => clk_S,
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enable => enable_S,
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selectb => bypass_mwd_S,
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a => short_S,
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b => data_in_S,
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data_valid => mwd_switch_data_valid_S,
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q => mwd_switch_out_S
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);
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reshape : shaper
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port map(rst => rst_S,
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clk => clk_S,
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enable => mwd_switch_data_valid_S,
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program => program_S,
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data_in => mwd_switch_out_S,
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correction_in => reshape_correction_S,
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data_out => reshaped_S
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);
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reshape_switch : mux_sre
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port map(rst => rst_S,
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clk => clk_S,
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enable => mwd_switch_data_valid_S,
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selectb => bypass_reshape_S,
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a => reshaped_S,
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b => mwd_switch_out_S,
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data_valid => reshape_switch_data_valid_S,
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q => reshape_switch_out_S
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);
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CF : CF_process
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generic map(WIDTH => SIGNED_WIDTH,
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MAX_CF_PWR => MAX_CF_PWR,
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MAX_BASELINE_PWR => MAX_BASELINE_PWR,
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ZEROX_WINDOW_PWR => ZEROX_WINDOW_PWR,
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ZEROX_THRESHOLD_PWR => ZEROX_THRESHOLD_PWR,
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INTERP_CYCLES => INTERP_CYCLES
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)
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PORT MAP( rst => rst_S,
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clk => clk_S,
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enable => reshape_switch_data_valid_S,
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program => program_S,
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baseline_enable => baseline_enable_S,
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double_CF_in => double_CF_S,
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data_in => reshape_switch_out_S,
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threshold_in => threshold_S,
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cf_pwr_in => cf_pwr_S,
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cf_integral_pwr_in => cf_integral_pwr_S,
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baseline_pwr_in => baseline_pwr_S,
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baseline_inhibit_cnt_in => baseline_inhibit_cnt_S,
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event_inhibit_cnt_in => event_inhibit_cnt_S,
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baseline_out => baseline_S,
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| 285 |
|
|
clamped_out => clamped_S,
|
| 286 |
|
|
del_clamp_out => del_clamp_S,
|
| 287 |
|
|
CFdev_clamp_out => CFdev_clamp_S,
|
| 288 |
|
|
cf_trace_out => cf_trace_S,
|
| 289 |
|
|
integral => integral_S,
|
| 290 |
|
|
sample_nr => sample_nr_S,
|
| 291 |
|
|
zeroX_out => zeroX_S,
|
| 292 |
|
|
event_detect_out => event_detect_S,
|
| 293 |
|
|
bl_gate_out => bl_gate_S,
|
| 294 |
|
|
ed_gate_out => ed_gate_S,
|
| 295 |
|
|
eventdata_valid => eventdata_valid_S,
|
| 296 |
|
|
eventnr_out => eventnr_S,
|
| 297 |
|
|
fraction => fraction_S,
|
| 298 |
|
|
energy => energy_S
|
| 299 |
|
|
);
|
| 300 |
|
|
|
| 301 |
|
|
rst_S <= rst;
|
| 302 |
|
|
clk_S <= clk;
|
| 303 |
|
|
program_S <= program;
|
| 304 |
|
|
baseline_enable_S <= baseline_enable;
|
| 305 |
|
|
double_CF_S <= double_CF_in;
|
| 306 |
|
|
bypass_mwd_S <= bypass_mwd;
|
| 307 |
|
|
bypass_reshape_S <= bypass_reshape;
|
| 308 |
|
|
invert_data_in_S <= invert_data_in;
|
| 309 |
|
|
|
| 310 |
|
|
data_in_S <= conv_std_logic_vector(conv_integer(unsigned(udata_in_S)), SIGNED_WIDTH) when invert_data_in_S = '0'
|
| 311 |
|
|
else conv_std_logic_vector(- conv_integer(unsigned(udata_in_S)), SIGNED_WIDTH);
|
| 312 |
|
|
|
| 313 |
|
|
decay_correction_S <= decay_correction_in;
|
| 314 |
|
|
reshape_correction_S <= reshape_correction_in;
|
| 315 |
|
|
threshold_S <= '0' & threshold_in; -- now it's 17 bit
|
| 316 |
|
|
mwd_pwr_S <= mwd_pwr_in;
|
| 317 |
|
|
cf_pwr_S <= cf_pwr_in;
|
| 318 |
|
|
cf_integral_pwr_S <= cf_integral_pwr_in;
|
| 319 |
|
|
baseline_pwr_S <= baseline_pwr_in;
|
| 320 |
|
|
baseline_inhibit_cnt_S <= baseline_inhibit_cnt_in;
|
| 321 |
|
|
event_inhibit_cnt_S <= event_inhibit_cnt_in;
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
mwd_switch_out <= reshape_switch_out_S;
|
| 325 |
|
|
baseline_out <= baseline_S;
|
| 326 |
|
|
clamped_out <= clamped_S;
|
| 327 |
|
|
del_clamp_out <= del_clamp_S;
|
| 328 |
|
|
CFdev_clamp_out <= CFdev_clamp_S;
|
| 329 |
|
|
cf_trace_out <= cf_trace_S;
|
| 330 |
|
|
integral <= integral_S;
|
| 331 |
|
|
sample_nr <= sample_nr_S;
|
| 332 |
|
|
zeroX_out <= zeroX_S;
|
| 333 |
|
|
event_detect_out <= event_detect_S;
|
| 334 |
|
|
bl_gate_out <= bl_gate_S;
|
| 335 |
|
|
ed_gate_out <= ed_gate_S;
|
| 336 |
|
|
eventdata_valid <= eventdata_valid_S;
|
| 337 |
|
|
eventnr_out <= eventnr_S;
|
| 338 |
|
|
fraction <= fraction_S;
|
| 339 |
|
|
energy <= energy_S;
|
| 340 |
|
|
|
| 341 |
|
|
-- fb_window_size <= fb_window_size_S;
|
| 342 |
|
|
|
| 343 |
|
|
-----------------------------------------------------------------------------------
|
| 344 |
|
|
|
| 345 |
|
|
-- sync : process(clk_S) -- introduced to compensate for synchronous resets (1 clock cycle delay)
|
| 346 |
|
|
-- begin
|
| 347 |
|
|
-- if (clk_S'event and clk_S = '1') then
|
| 348 |
|
|
enable_S <= enable;
|
| 349 |
|
|
udata_in_S <= data_in; -- add a sign bit to avoid disaster
|
| 350 |
|
|
-- end if;
|
| 351 |
|
|
-- end process;
|
| 352 |
|
|
|
| 353 |
|
|
end Behavioral;
|
