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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : control_feedback.vhd
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-- Description : This module is for debugging purposes only.
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-- Unused vme-registers are used to readback settings/signals for basic debugging
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity control_feedback is
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port( rst : in std_logic;
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ADclk : in std_logic;
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uPclk : in std_logic;
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cmd_output_select : in std_logic_vector(3 downto 0);
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buffersize : in std_logic_vector(31 downto 0);
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chain_enable : in std_logic;
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flowctrl_running : in std_logic;
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output_select_valid : in std_logic;
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fb_output_select : out std_logic_vector(3 downto 0);
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fb_buffersize : out std_logic_vector(31 downto 0);
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fb_chain_enable : out std_logic;
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fb_running : out std_logic;
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fb_output_valid : out std_logic
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);
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end control_feedback;
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architecture Behavioral of control_feedback is
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signal rst_S : std_logic := '1';
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signal ADclk_S : std_logic := '0';
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signal uPclk_S : std_logic := '0';
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signal cmd_output_select_S : std_logic_vector(3 downto 0) := (others => '0');
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signal buffersize_S : std_logic_vector(31 downto 0) := (others => '0');
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signal chain_enable_S : std_logic := '0';
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signal running_S : std_logic := '0';
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signal output_valid_S : std_logic := '0';
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signal fb_output_select_S : std_logic_vector(3 downto 0) := (others => '0');
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signal fb_buffersize_S : std_logic_vector(31 downto 0) := (others => '0');
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signal fb_chain_enable_S : std_logic := '0';
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signal fb_running_S : std_logic := '0';
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signal fb_output_valid_S : std_logic := '0';
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begin
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rst_S <= rst;
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ADclk_S <= ADclk;
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uPclk_S <= uPclk;
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AD_sync : process(ADclk_S)
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begin
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if rising_edge(ADclk_S) then
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cmd_output_select_S <= cmd_output_select;
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buffersize_S <= buffersize;
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chain_enable_S <= chain_enable;
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running_S <= flowctrl_running;
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output_valid_S <= output_select_valid;
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end if;
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end process;
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feedback : process(uPclk_S, rst_S)
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begin
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if rising_edge(uPclk_S) then
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if (rst_S = '1') then
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fb_output_select <= (others => '0');
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fb_buffersize <= (others => '0');
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fb_chain_enable <= '0';
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fb_running <= '0';
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fb_output_valid <= '0';
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else
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fb_output_select_S <= cmd_output_select_S;
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fb_buffersize_S <= buffersize_S;
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fb_chain_enable_S <= chain_enable_S;
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fb_running_S <= running_S;
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fb_output_valid_S <= output_valid_S;
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----------------------------------------------------------
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fb_output_select <= fb_output_select_S;
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fb_buffersize <= fb_buffersize_S;
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fb_chain_enable <= fb_chain_enable_S;
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fb_running <= fb_running_S;
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fb_output_valid <= fb_output_valid_S;
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end if;
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end if;
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end process;
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end Behavioral;
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