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--******************************************************************************

--

--  Xilinx, Inc. 2002                 www.xilinx.com

--

--

--*******************************************************************************

--

--  File name :       data_path.vhd

--

--  Description :     This module comprises the write and read data paths for the

--                    DDR1 memory interface. The write data along with write enable 

--                    signals are forwarded to the DDR IOB FFs. The read data is 

--                    captured in CLB FFs and finally input to FIFOs.

-- 

--                    

--  Date - revision : 10/16/2003

--

--

-- 

--*****************************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

--library synplify; 

--use synplify.attributes.all;

--

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

entity data_path_rst is

port(

     clk                : in std_logic;

     clk180             : in std_logic;

     clk90              : in std_logic;

     reset              : in std_logic;

     reset90            : in std_logic;

     reset180           : in std_logic;

     reset270           : in std_logic;

     reset_r            : out std_logic;

     reset90_r          : out std_logic;

     reset90_r1         : out std_logic;

     reset180_r         : out std_logic;

     reset270_r         : out std_logic

     );

end data_path_rst;

architecture arc_data_path_rst of data_path_rst is

attribute syn_keep : boolean;

  component FD

    port(

      Q                              : out STD_LOGIC;

      C                              : in STD_LOGIC;

      D                              : in STD_LOGIC

      );

  end component;

signal clk270    : std_logic;

--attribute syn_keep of clk270 : signal is true;

begin

-- ********************************

--  generation of clk180 and clk270

-- *********************************

 clk270 <= not clk90;

--***********************************************************************

-- Reset flip-flops

--***********************************************************************

rst0_r : FD port map (

                      Q => reset_r,

                      C => clk,

                      D => reset

                      );

rst90_r : FD port map (

                      Q => reset90_r,

                      C => clk90,

                      D => reset90

                      );

rst90_r1 : FD port map (

                      Q => reset90_r1,

                      C => clk90,

                      D => reset90

                      );

rst180_r : FD port map (

                      Q => reset180_r,

                      C => clk180,

                      D => reset180

                      );

rst270_r : FD port map (

                      Q => reset270_r,

                      C => clk270,

                      D => reset270

                      );

end arc_data_path_rst;