Subversion Repositories pulse_processing_algorithm

--*********************************************************************

-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins

-- In the current DATA PATH logic DATA CAPTURE part was modified.

-- The below changes were made to reduce the resources in 

-- the data capture

-- in the current architecture data ( dq ) from ddr memory 

-- directly stored into the FIFO's.

-- Architectural changes :

-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 

-- Used Single col ( col0 ) dqs_delayed_col signals

-- Used Gray Counters for write and read pointers of the FIFOs 

-- fbit stage is removed from ddr1_dqbit module ( in the data capture )

-- dq_clk stage was removed 

-- dqs_clk_div logic was removed

-- ddr1_transfer_done logic was removed 

-- data valid signals registering in clk90 domain was removed

-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain

-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  

-- write enable for the FIFOs derived from rst_dqs_div signal

--*********************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

--library synplify; 

--use synplify.attributes.all;

--

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

entity data_write is

port(

     user_input_data    : in std_logic_vector(31 downto 0);

     clk90              : in std_logic;

     reset90_r          : in std_logic;

     reset270_r         : in std_logic;

     write_enable       : in std_logic;

     write_en_val       : out std_logic;

     write_en_val1      : out std_logic;

     write_data_falling : out std_logic_vector(15 downto 0);

     write_data_rising  : out std_logic_vector(15 downto 0);

     data_mask_f        : out std_logic_vector(1 downto 0);

     data_mask_r        : out std_logic_vector(1 downto 0)

     );

end data_write;

architecture arc_data_write of data_write is

attribute syn_noprune : boolean;  -- Using Syn_noprune Derictive

signal write_en_P1            : std_logic;

signal write_en_P2            : std_logic;

--PL

--signal write_en_P3            : std_logic;

--PL

--signal write_en_int           : std_logic;

signal write_data             : std_logic_vector(15 downto 0);

signal write_data1            : std_logic_vector(31 downto 0);

signal write_data2            : std_logic_vector(31 downto 0);

signal write_data3            : std_logic_vector(31 downto 0);

signal write_data4            : std_logic_vector(31 downto 0);

signal write_data5            : std_logic_vector(31 downto 0);

signal write_data6            : std_logic_vector(15 downto 0);

signal write_data_int         : std_logic_vector(31 downto 0);

signal write_data270_1        : std_logic_vector(15 downto 0);

signal write_data270_2        : std_logic_vector(15 downto 0);

--attribute syn_noprune of write_en_val : signal is true;

--attribute syn_noprune of write_en_val1 : signal is true;

begin

data_mask_f <= "00";

data_mask_r <= "00";

-- data path for write enable

process(clk90)

begin

  if clk90'event and clk90 = '1' then

   if reset90_r = '1' then

    write_en_P1 <= '0';

    write_en_P2 <= '0';

--PL

--    write_en_P3 <= '0';

   else

     write_en_P1 <= write_enable;

     write_en_P2 <= write_en_P1;

--PL

--     write_en_P3 <= write_en_P2;

   end if;

  end if;

end process;

--- the following lines have been replaced for timing reasons. 

--- One stage of the write_en_val has been moved to datapath_iobs

-- data path for write enable

--process(clk90)

--begin

-- if clk90'event and clk90 = '0' then

--  if reset90_r = '1' then

--    write_en_int    <= '0';

--    write_en_val    <= '0';

--    write_en_val1   <= '0';

--  else

--     write_en_int   <= write_en_P2;

--     write_en_val  <= write_en_int;

--     write_en_val1  <= write_en_p3; -- assinged for reducing fan-out 

--  end if;

-- end if;

--end process;

process(clk90)

begin

 if clk90'event and clk90 = '0' then

  if reset90_r = '1' then

--PL

--    write_en_int    <= '0';

    write_en_val    <= '0';

    write_en_val1   <= '0';

  else

--     write_en_int   <= write_en_P2;

     write_en_val  <= write_en_p2;

     write_en_val1  <= write_en_p2; -- assinged for reducing fan-out 

  end if;

 end if;

end process;

process(clk90)

begin

  if clk90'event and clk90 = '1' then

    if reset90_r = '1' then

       write_data_int   <= (others => '0');

       write_data1      <= (others => '0');

       write_data2      <= (others => '0');

       write_data3      <= (others => '0');

       write_data4      <= (others => '0');

       write_data5      <= (others => '0');

       write_data6      <= (others => '0');

       write_data       <= (others => '0');

    else

       write_data_int         <= user_input_data(31 downto 0);

       write_data1            <= write_data_int;

       write_data2            <= write_data1;

       write_data3            <= write_data2;

       write_data4            <= write_data3;

       write_data5            <= write_data4;

       write_data6            <= write_data5(15 downto 0);

       write_data             <= write_data6;

    end if;

  end if;

end process;

process(clk90)

begin

  if clk90'event and clk90 = '1' then

    if reset90_r = '1' then

       write_data270_1  <= (others => '0');

       write_data270_2  <= (others => '0');

    else

       write_data270_1  <= write_data5(31 downto 16);

       write_data270_2  <= write_data270_1;

    end if;

  end if;

end process;

write_data_rising  <= write_data270_2;

write_data_falling <= write_data(15 downto 0);

end arc_data_write;