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panda_emc |
--******************************************************************************
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--
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-- Xilinx, Inc. 2002 www.xilinx.com
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--
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--
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--*******************************************************************************
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--
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-- File name : ddr2_data_path.vhd
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--
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-- Description : This module comprises the write and read data paths for the
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-- DDR1 memory interface. The write data along with write enable
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-- signals are forwarded to the DDR IOB FFs. The read data is
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-- captured in CLB FFs and finally input to FIFOs.
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--
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--
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-- Date - revision : 10/16/2003
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--
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--
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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--library synplify;
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--use synplify.attributes.all;
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--
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-- pragma translate_off
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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-- pragma translate_on
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--
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entity ddr2_data_path is
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port(
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user_input_data : in std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk180 : IN std_logic;
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clk90 : in std_logic;
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reset : in std_logic;
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reset90 : in std_logic;
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reset180 : in std_logic;
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reset270 : in std_logic;
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write_enable : in std_logic;
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rst_dqs_div_in : in std_logic;
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delay_sel : in std_logic_vector(4 downto 0);
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dqs_int_delay_in0 : in std_logic;
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dqs_int_delay_in1 : in std_logic;
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-- dq_in : in std_logic_vector(15 downto 0);
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dq_in_rising : in std_logic_vector(15 downto 0);
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dq_in_falling : in std_logic_vector(15 downto 0);
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u_data_val : out std_logic;
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user_output_data : out std_logic_vector(31 downto 0);
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write_en_val : out std_logic;
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write_en_val1 : out std_logic;
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reset90_r_val : out std_logic;
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data_mask_f : out std_logic_vector(1 downto 0);
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data_mask_r : out std_logic_vector(1 downto 0);
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write_data_falling : out std_logic_vector(15 downto 0);
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write_data_rising : out std_logic_vector(15 downto 0);
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test_fifo_wr_addr: out std_logic_vector(15 downto 0)
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);
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end ddr2_data_path;
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architecture arc_ddr2_data_path of ddr2_data_path is
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component data_read
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port(
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clk90 : in std_logic;
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reset90_r : in std_logic;
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--old ddr_dq_in : in std_logic_vector(15 downto 0);
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ddr_dq_in_rising : in std_logic_vector(15 downto 0);
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ddr_dq_in_falling : in std_logic_vector(15 downto 0);
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read_valid_data_1 : in std_logic;
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fifo_00_wr_en : in std_logic;
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fifo_10_wr_en : in std_logic;
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fifo_01_wr_en : in std_logic;
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fifo_11_wr_en : in std_logic;
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fifo_00_wr_addr : in std_logic_vector(3 downto 0);
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fifo_01_wr_addr : in std_logic_vector(3 downto 0);
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fifo_10_wr_addr : in std_logic_vector(3 downto 0);
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fifo_11_wr_addr : in std_logic_vector(3 downto 0);
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-- dqs0_delayed_col1 : in std_logic;
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-- dqs1_delayed_col1 : in std_logic;
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dqs0_delayed_col0 : in std_logic;
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dqs1_delayed_col0 : in std_logic;
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user_output_data : out std_logic_vector(31 downto 0);
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fifo0_rd_addr_val: out std_logic_vector(3 downto 0);
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fifo1_rd_addr_val: out std_logic_vector(3 downto 0)
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);
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end component;
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component data_read_controller
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port(
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clk90 : in std_logic;
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clk180 : in std_logic;
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reset_r : in std_logic;
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reset90_r : in std_logic;
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rst_dqs_div_in : in std_logic;
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delay_sel : in std_logic_vector(4 downto 0);
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dqs_int_delay_in0 : in std_logic;
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dqs_int_delay_in1 : in std_logic;
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fifo0_rd_addr : in std_logic_vector(3 downto 0);
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fifo1_rd_addr : in std_logic_vector(3 downto 0);
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u_data_val : out std_logic;
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read_valid_data_1_val : out std_logic;
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fifo_00_wr_en_val : out std_logic;
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fifo_10_wr_en_val : out std_logic;
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fifo_01_wr_en_val : out std_logic;
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fifo_11_wr_en_val : out std_logic;
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fifo_00_wr_addr_val : out std_logic_vector(3 downto 0);
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fifo_01_wr_addr_val : out std_logic_vector(3 downto 0);
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fifo_10_wr_addr_val : out std_logic_vector(3 downto 0);
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fifo_11_wr_addr_val : out std_logic_vector(3 downto 0);
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dqs0_delayed_col0_val : out std_logic;
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dqs1_delayed_col0_val : out std_logic
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-- dqs0_delayed_col1_val : out std_logic;
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-- dqs1_delayed_col1_val : out std_logic
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);
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end component;
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component data_write
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port(
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user_input_data : in std_logic_vector(31 downto 0);
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clk90 : in std_logic;
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reset90_r : in std_logic;
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reset270_r : in std_logic;
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write_enable : in std_logic;
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write_en_val : out std_logic;
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write_en_val1 : out std_logic;
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write_data_falling : out std_logic_vector(15 downto 0);
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write_data_rising : out std_logic_vector(15 downto 0);
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data_mask_f : out std_logic_vector(1 downto 0);
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data_mask_r : out std_logic_vector(1 downto 0)
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);
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end component;
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component data_path_rst
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port(
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clk : in std_logic;
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clk180 : in std_logic;
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clk90 : in std_logic;
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reset : in std_logic;
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reset90 : in std_logic;
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reset180 : in std_logic;
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reset270 : in std_logic;
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reset_r : out std_logic;
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reset90_r : out std_logic;
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reset90_r1 : out std_logic;
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reset180_r : out std_logic;
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reset270_r : out std_logic
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);
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end component;
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signal reset_r : std_logic;
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signal reset90_r : std_logic;
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signal reset90_r1 : std_logic;
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signal reset180_r : std_logic;
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signal reset270_r : std_logic;
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signal fifo0_rd_addr : std_logic_vector(3 downto 0);
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signal fifo1_rd_addr : std_logic_vector(3 downto 0);
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signal read_valid_data_1 : std_logic;
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signal fifo_00_wr_addr : std_logic_vector(3 downto 0);
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signal fifo_01_wr_addr : std_logic_vector(3 downto 0);
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signal fifo_10_wr_addr : std_logic_vector(3 downto 0);
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signal fifo_11_wr_addr : std_logic_vector(3 downto 0);
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signal fifo_00_wr_en : std_logic;
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signal fifo_10_wr_en : std_logic;
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signal fifo_01_wr_en : std_logic;
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signal fifo_11_wr_en : std_logic;
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-- signal dqs0_delayed_col1 : std_logic;
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-- signal dqs1_delayed_col1 : std_logic;
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signal dqs0_delayed_col0 : std_logic;
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signal dqs1_delayed_col0 : std_logic;
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Function to_std_logic(X: in Boolean) return Std_Logic is
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variable ret : std_logic;
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begin
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if x then ret := '1'; else ret := '0'; end if;
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return ret;
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end to_std_logic;
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attribute syn_keep : boolean; -- Using Syn_Keep Derictive
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--signal tclk180_fifo_01_wr_en: std_logic;
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--signal tclk180_fifo_01_wr_en_delay1: std_logic;
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--signal tclk180_fifo_01_wr_en_delay2: std_logic;
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--signal tclk180_fifo_01_wr_en_delay3: std_logic;
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--signal tclk180_fifo_01_wr_en_delay4: std_logic;
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--signal tclk180_fifo_01_wr_en_delay5: std_logic;
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--signal tclk180_fifo_01_wr_en_delay6: std_logic;
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--signal tclk180_fifo_01_wr_en_delay7: std_logic;
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--signal tclk180_fifo_01_wr_en_delay8: std_logic;
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--signal tclk180_fifo_01_wr_en_delay9: std_logic;
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--signal tclk180_fifo_01_wr_en_end_pulse: std_logic;
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--signal tclk180_fifo_01_00_neq_flag: std_logic;
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--signal tclk180_fifo_11_wr_en: std_logic;
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--signal tclk180_fifo_11_wr_en_delay1: std_logic;
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--signal tclk180_fifo_11_wr_en_delay2: std_logic;
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--signal tclk180_fifo_11_wr_en_delay3: std_logic;
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--signal tclk180_fifo_11_wr_en_delay4: std_logic;
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--signal tclk180_fifo_11_wr_en_delay5: std_logic;
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--signal tclk180_fifo_11_wr_en_delay6: std_logic;
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--signal tclk180_fifo_11_wr_en_delay7: std_logic;
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--signal tclk180_fifo_11_wr_en_delay8: std_logic;
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--signal tclk180_fifo_11_wr_en_delay9: std_logic;
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--signal tclk180_fifo_11_wr_en_end_pulse: std_logic;
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--PL: om een warning te lozen
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--signal tclk180_fifo_11_10_neq_flag: std_logic;
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--attribute syn_keep of tclk180_fifo_01_wr_en_end_pulse : signal is true;
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--attribute syn_keep of tclk180_fifo_01_00_neq_flag : signal is true;
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--PL: om een warning te lozen
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--attribute syn_keep of tclk180_fifo_11_wr_en_end_pulse : signal is true;
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--PL: om een warning te lozen
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--attribute syn_keep of tclk180_fifo_11_10_neq_flag : signal is true;
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begin
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-- test
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--PL alles commentaar want dit zijn 2 schuifregisters naar nergens
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test_fifo_logic: process(clk180)
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begin
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-- if rising_edge (clk180) then
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-- tclk180_fifo_01_wr_en <= fifo_01_wr_en ;
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-- tclk180_fifo_01_wr_en_delay1 <= tclk180_fifo_01_wr_en ;
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-- tclk180_fifo_01_wr_en_delay2 <= tclk180_fifo_01_wr_en_delay1 ;
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-- tclk180_fifo_01_wr_en_delay3 <= tclk180_fifo_01_wr_en_delay2 ;
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-- tclk180_fifo_01_wr_en_delay4 <= tclk180_fifo_01_wr_en_delay3 ;
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-- tclk180_fifo_01_wr_en_delay5 <= tclk180_fifo_01_wr_en_delay4 ;
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-- tclk180_fifo_01_wr_en_delay6 <= tclk180_fifo_01_wr_en_delay5 ;
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-- tclk180_fifo_01_wr_en_delay7 <= tclk180_fifo_01_wr_en_delay6 ;
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-- tclk180_fifo_01_wr_en_delay8 <= tclk180_fifo_01_wr_en_delay7 ;
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-- tclk180_fifo_01_wr_en_delay9 <= tclk180_fifo_01_wr_en_delay8 ;
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-- tclk180_fifo_01_wr_en_end_pulse <= tclk180_fifo_01_wr_en_delay9 and not tclk180_fifo_01_wr_en_delay8;
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-- end if;
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--PL: om een warning te lozen
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-- if rising_edge (clk180) then
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-- tclk180_fifo_01_00_neq_flag <= tclk180_fifo_01_wr_en_end_pulse and to_std_logic( fifo_01_wr_addr /= fifo_00_wr_addr) ;
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-- end if;
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-- if rising_edge (clk180) then
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-- tclk180_fifo_11_wr_en <= fifo_11_wr_en ;
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-- tclk180_fifo_11_wr_en_delay1 <= tclk180_fifo_11_wr_en ;
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-- tclk180_fifo_11_wr_en_delay2 <= tclk180_fifo_11_wr_en_delay1 ;
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-- tclk180_fifo_11_wr_en_delay3 <= tclk180_fifo_11_wr_en_delay2 ;
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-- tclk180_fifo_11_wr_en_delay4 <= tclk180_fifo_11_wr_en_delay3 ;
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-- tclk180_fifo_11_wr_en_delay5 <= tclk180_fifo_11_wr_en_delay4 ;
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-- tclk180_fifo_11_wr_en_delay6 <= tclk180_fifo_11_wr_en_delay5 ;
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-- tclk180_fifo_11_wr_en_delay7 <= tclk180_fifo_11_wr_en_delay6 ;
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-- tclk180_fifo_11_wr_en_delay8 <= tclk180_fifo_11_wr_en_delay7 ;
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-- tclk180_fifo_11_wr_en_delay9 <= tclk180_fifo_11_wr_en_delay8 ;
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-- tclk180_fifo_11_wr_en_end_pulse <= tclk180_fifo_11_wr_en_delay9 and not tclk180_fifo_11_wr_en_delay8;
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-- end if;
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--PL: om een warning te lozen
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-- if rising_edge (clk180) then
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-- tclk180_fifo_11_10_neq_flag <= tclk180_fifo_11_wr_en_end_pulse and to_std_logic( fifo_11_wr_addr /= fifo_10_wr_addr) ;
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-- end if;
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if rising_edge (clk180) then
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test_fifo_wr_addr(15 downto 12) <= fifo_11_wr_addr(3 downto 0) ;
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test_fifo_wr_addr(11 downto 8) <= fifo_10_wr_addr(3 downto 0) ;
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test_fifo_wr_addr(7 downto 4) <= fifo_01_wr_addr(3 downto 0) ;
|
309 |
|
|
test_fifo_wr_addr(3 downto 0) <= fifo_00_wr_addr(3 downto 0) ;
|
310 |
|
|
end if;
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
end process;
|
316 |
|
|
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
reset90_r_val <= reset90_r;
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
data_read0 : data_read
|
323 |
|
|
port map (
|
324 |
|
|
clk90 => clk90,
|
325 |
|
|
reset90_r => reset90_r1,
|
326 |
|
|
ddr_dq_in_rising => dq_in_rising,
|
327 |
|
|
ddr_dq_in_falling => dq_in_falling,
|
328 |
|
|
read_valid_data_1 => read_valid_data_1,
|
329 |
|
|
|
330 |
|
|
fifo_00_wr_en => fifo_00_wr_en,
|
331 |
|
|
fifo_10_wr_en => fifo_10_wr_en,
|
332 |
|
|
|
333 |
|
|
fifo_01_wr_en => fifo_01_wr_en,
|
334 |
|
|
fifo_11_wr_en => fifo_11_wr_en,
|
335 |
|
|
|
336 |
|
|
fifo_00_wr_addr => fifo_00_wr_addr,
|
337 |
|
|
fifo_01_wr_addr => fifo_01_wr_addr,
|
338 |
|
|
fifo_10_wr_addr => fifo_10_wr_addr,
|
339 |
|
|
fifo_11_wr_addr => fifo_11_wr_addr,
|
340 |
|
|
|
341 |
|
|
dqs0_delayed_col0 => dqs0_delayed_col0,
|
342 |
|
|
dqs1_delayed_col0 => dqs1_delayed_col0,
|
343 |
|
|
|
344 |
|
|
user_output_data => user_output_data,
|
345 |
|
|
fifo0_rd_addr_val => fifo0_rd_addr,
|
346 |
|
|
fifo1_rd_addr_val => fifo1_rd_addr
|
347 |
|
|
);
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
data_read_controller0 : data_read_controller
|
351 |
|
|
port map (
|
352 |
|
|
clk90 => clk90,
|
353 |
|
|
clk180 => clk180,
|
354 |
|
|
reset_r => reset_r,
|
355 |
|
|
reset90_r => reset90_r1,
|
356 |
|
|
rst_dqs_div_in => rst_dqs_div_in,
|
357 |
|
|
delay_sel => delay_sel,
|
358 |
|
|
dqs_int_delay_in0 => dqs_int_delay_in0,
|
359 |
|
|
dqs_int_delay_in1 => dqs_int_delay_in1,
|
360 |
|
|
|
361 |
|
|
fifo0_rd_addr => fifo0_rd_addr,
|
362 |
|
|
fifo1_rd_addr => fifo1_rd_addr,
|
363 |
|
|
u_data_val => u_data_val,
|
364 |
|
|
read_valid_data_1_val => read_valid_data_1,
|
365 |
|
|
|
366 |
|
|
fifo_00_wr_en_val => fifo_00_wr_en,
|
367 |
|
|
fifo_10_wr_en_val => fifo_10_wr_en,
|
368 |
|
|
|
369 |
|
|
fifo_01_wr_en_val => fifo_01_wr_en,
|
370 |
|
|
fifo_11_wr_en_val => fifo_11_wr_en,
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
fifo_00_wr_addr_val => fifo_00_wr_addr,
|
374 |
|
|
fifo_01_wr_addr_val => fifo_01_wr_addr,
|
375 |
|
|
fifo_10_wr_addr_val => fifo_10_wr_addr,
|
376 |
|
|
fifo_11_wr_addr_val => fifo_11_wr_addr,
|
377 |
|
|
|
378 |
|
|
dqs0_delayed_col0_val => dqs0_delayed_col0,
|
379 |
|
|
dqs1_delayed_col0_val => dqs1_delayed_col0
|
380 |
|
|
|
381 |
|
|
);
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
data_write0 : data_write
|
385 |
|
|
port map (
|
386 |
|
|
user_input_data => user_input_data,
|
387 |
|
|
clk90 => clk90,
|
388 |
|
|
reset90_r => reset90_r1,
|
389 |
|
|
reset270_r => reset270_r,
|
390 |
|
|
write_enable => write_enable,
|
391 |
|
|
write_en_val => write_en_val,
|
392 |
|
|
write_en_val1 => write_en_val1,
|
393 |
|
|
write_data_falling => write_data_falling,
|
394 |
|
|
write_data_rising => write_data_rising,
|
395 |
|
|
data_mask_f => data_mask_f,
|
396 |
|
|
data_mask_r => data_mask_r
|
397 |
|
|
);
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
data_path_rst0 : data_path_rst
|
401 |
|
|
port map (
|
402 |
|
|
clk => clk,
|
403 |
|
|
clk180 => clk180,
|
404 |
|
|
clk90 => clk90,
|
405 |
|
|
reset => reset,
|
406 |
|
|
reset90 => reset90,
|
407 |
|
|
reset180 => reset180,
|
408 |
|
|
reset270 => reset270,
|
409 |
|
|
reset_r => reset_r,
|
410 |
|
|
reset90_r => reset90_r,
|
411 |
|
|
reset90_r1 => reset90_r1,
|
412 |
|
|
reset180_r => reset180_r,
|
413 |
|
|
reset270_r => reset270_r
|
414 |
|
|
);
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
end arc_ddr2_data_path;
|