Subversion Repositories pulse_processing_algorithm

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--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

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-- Company              :       KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author               :       P.J.J. Lemmens

-- Design Name  :       Feature Extraction

-- Module Name  :       adc_flow_control.vhd

-- Description  :       The SIS3301/2 shares memory between the ADCs and VME. On the adc side

--                                              each controlling fpga gets a base address and a chunk of memory to write into.

--                                              The memory is not directly written into but through a pair of FIFOs; one

--                                              for the data (32bit) and one for the address(32 bit) to which you want to

--                                              write. This module builds 32-bit words for the data fifo from 16-bit words

--                                              of data from the signal-processing. This module provides the addresses from

--                                              the base-address to the end of the ringbuffer (baseaddress + buffersize)

--                                              When reset, restarted or reprogrammed, the address-generator is reset,

--                                              beginning at the base-address.

--                                              

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ddr_address_generator is

        port(   clk                                     : in    std_logic;

                        rst                                     : in    std_logic;

                        enable                          : in    std_logic;

                        program                         : in    std_logic;

                        restart                         : in    std_logic;

                        base_address_in : in    std_logic_vector;

                        buffersize_in           : in    std_logic_vector;

                        address_out                     : out   std_logic_vector

                );

end ddr_address_generator;

architecture Behavioral of ddr_address_generator is

        constant WIDTH                          : natural       := base_address_in'length;

        signal clk_S                            : std_logic := '0';

   signal rst_S                         : std_logic := '1';

        signal enable_S                 : std_logic := '0';

        signal program_S                        : std_logic := '0';

   signal restart_S                     : std_logic := '1';

        signal base_address_S   : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal buffersize_S             : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal max_address_S            : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal address_out_S            : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

begin

        clk_S                                                                   <= clk;

        rst_S                                                                   <= rst;

        enable_S                                                                <= enable;

        program_S                                                       <=      program;

        restart_S                                                       <= restart;

        base_address_S                                          <= base_address_in;

        buffersize_S                                            <= buffersize_in;

        address_out                                                     <= address_out_S;

        address_gen     : process(clk_S)

        begin

                if rising_edge(clk_S) then

                        if (rst_S = '1') or (program_S = '1') or (restart_S = '1') then

                                address_out_S   <= base_address_S;

                                max_address_S   <= conv_std_logic_vector((conv_integer(base_address_S) + conv_integer(buffersize_S) - 1), 32);

                        else

                                if (enable_S = '1') then

                                        if (address_out_S = max_address_S) then

                                                address_out_S   <= base_address_S;

                                        else

                                                address_out_S   <= address_out_S + 1;

                                        end if;

                                end if;

                        end if;

                end if;

        end process;

end Behavioral;