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[/] [pulse_processing_algorithm/] [rd_gray_cntr.vhd] - Blame information for rev 2

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-- fifo_rd_addr gray counter with synchronous reset
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
 
 
ENTITY  rd_gray_cntr IS
        port (
                        clk                             :       in std_logic;
                        reset                           :       in std_logic;
                        cnt_en                          :       in std_logic;
                        rgc_gcnt                        :       out     std_logic_vector(3 downto 0)
 
                  );
END rd_gray_cntr;
 
ARCHITECTURE rd_gray_cntr OF rd_gray_cntr IS
 
component FDRE
    port(
      Q                              :  out   STD_ULOGIC;
      C                              :  in    STD_ULOGIC;
      CE                             :  in    STD_ULOGIC;
      D                              :  in    STD_ULOGIC;
      R                              :  in    STD_ULOGIC
      );
end component;
 
-- gray encoded signals
 
signal  d0      :       STD_ULOGIC;
signal  d1      :       STD_ULOGIC;
signal  d2      :       STD_ULOGIC;
signal  d3      :       STD_ULOGIC;
signal  gc_int0 :  std_logic_vector(3 downto 0);
 
 
BEGIN
 
    rgc_gcnt <= gc_int0(3 downto 0);
 
 
    d0 <= ( (not gc_int0(3)) and (not gc_int0(2)) and (not gc_int0(1)) ) or ( gc_int0(3) and gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(3) and (not gc_int0(2)) and gc_int0(1) ) or ( (not gc_int0(3)) and gc_int0(2) and gc_int0(1) );
    d1 <= ( gc_int0(1) and (not gc_int0(0)) ) or ( (not gc_int0(3)) and (not gc_int0(2)) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(2) and gc_int0(0) );
    d2 <= ( (not gc_int0(3)) and gc_int0(1) and (not gc_int0(0)) ) or ( gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(2) and gc_int0(0) );
    d3 <= ( gc_int0(2) and (not gc_int0(1)) and (not gc_int0(0)) ) or ( gc_int0(3) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(1) );
 
 
bit0 : FDRE port map (
                      Q   => gc_int0(0),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d0,
                            R   => reset
                     );
 
bit1 : FDRE port map (
                      Q   => gc_int0(1),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d1,
                            R   => reset
                     );
 
bit2 : FDRE port map (
                      Q   => gc_int0(2),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d2,
                            R   => reset
                     );
 
bit3 : FDRE port map (
                      Q   => gc_int0(3),
                      C   => clk,
                      CE  => cnt_en,
                      D   => d3,
                      R   => reset
                     );
 
END rd_gray_cntr;
 

Line No.	Rev	Author	Line
1	2	panda_emc	`-- fifo_rd_addr gray counter with synchronous reset`
2
3			`LIBRARY ieee;`
4			`USE ieee.std_logic_1164.all;`
5			`USE ieee.std_logic_arith.all;`
6
7			`-- pragma translate_off`
8			`library UNISIM;`
9			`use UNISIM.VCOMPONENTS.ALL;`
10			`-- pragma translate_on`
11			`--`
12
13
14
15			`ENTITY rd_gray_cntr IS`
16			`port (`
17			`clk : in std_logic;`
18			`reset : in std_logic;`
19			`cnt_en : in std_logic;`
20			`rgc_gcnt : out std_logic_vector(3 downto 0)`
21
22			`);`
23			`END rd_gray_cntr;`
24
25			`ARCHITECTURE rd_gray_cntr OF rd_gray_cntr IS`
26
27			`component FDRE`
28			`port(`
29			`Q : out STD_ULOGIC;`
30			`C : in STD_ULOGIC;`
31			`CE : in STD_ULOGIC;`
32			`D : in STD_ULOGIC;`
33			`R : in STD_ULOGIC`
34			`);`
35			`end component;`
36
37			`-- gray encoded signals`
38
39			`signal d0 : STD_ULOGIC;`
40			`signal d1 : STD_ULOGIC;`
41			`signal d2 : STD_ULOGIC;`
42			`signal d3 : STD_ULOGIC;`
43			`signal gc_int0 : std_logic_vector(3 downto 0);`
44
45
46			`BEGIN`
47
48			`rgc_gcnt <= gc_int0(3 downto 0);`
49
50
51			`d0 <= ( (not gc_int0(3)) and (not gc_int0(2)) and (not gc_int0(1)) ) or ( gc_int0(3) and gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(3) and (not gc_int0(2)) and gc_int0(1) ) or ( (not gc_int0(3)) and gc_int0(2) and gc_int0(1) );`
52			`d1 <= ( gc_int0(1) and (not gc_int0(0)) ) or ( (not gc_int0(3)) and (not gc_int0(2)) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(2) and gc_int0(0) );`
53			`d2 <= ( (not gc_int0(3)) and gc_int0(1) and (not gc_int0(0)) ) or ( gc_int0(2) and (not gc_int0(1)) ) or ( gc_int0(2) and gc_int0(0) );`
54			`d3 <= ( gc_int0(2) and (not gc_int0(1)) and (not gc_int0(0)) ) or ( gc_int0(3) and gc_int0(0) ) or ( gc_int0(3) and gc_int0(1) );`
55
56
57			`bit0 : FDRE port map (`
58			`Q => gc_int0(0),`
59			`C => clk,`
60			`CE => cnt_en,`
61			`D => d0,`
62			`R => reset`
63			`);`
64
65			`bit1 : FDRE port map (`
66			`Q => gc_int0(1),`
67			`C => clk,`
68			`CE => cnt_en,`
69			`D => d1,`
70			`R => reset`
71			`);`
72
73			`bit2 : FDRE port map (`
74			`Q => gc_int0(2),`
75			`C => clk,`
76			`CE => cnt_en,`
77			`D => d2,`
78			`R => reset`
79			`);`
80
81			`bit3 : FDRE port map (`
82			`Q => gc_int0(3),`
83			`C => clk,`
84			`CE => cnt_en,`
85			`D => d3,`
86			`R => reset`
87			`);`
88
89			`END rd_gray_cntr;`
90

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Subversion Repositories pulse_processing_algorithm

[/] [pulse_processing_algorithm/] [rd_gray_cntr.vhd] - Blame information for rev 2