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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company: KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author: P.J.J. Lemmens
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-- Design Name: Feature Extraction
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-- Module Name: mux_sre.vhd
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-- Description: fixed length (=2) MWD module to reshape slopes of MWD-pulses
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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entity shaper is
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in std_logic;
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data_in : in STD_LOGIC_VECTOR;
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correction_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR
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);
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end shaper;
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architecture Behavioral of shaper is
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constant WIDTH : natural := data_in'length;
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constant M_WIDTH : natural := 18; -- Multiplier width ; xilinx MULT18x18_SIO
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component SISO_add_a
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-- generic( WIDTH : natural);
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port (
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dataa : IN STD_LOGIC_VECTOR;
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datab : IN STD_LOGIC_VECTOR;
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result : OUT STD_LOGIC_VECTOR
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);
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end component;
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component SISO_sub_a
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generic( --WIDTH : natural;
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A_MINUS_B : boolean
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);
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port (
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dataa : IN STD_LOGIC_VECTOR;
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datab : IN STD_LOGIC_VECTOR;
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result : OUT STD_LOGIC_VECTOR
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);
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end component;
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component dff_re
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port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : IN STD_LOGIC := '1';
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d : in STD_LOGIC_VECTOR;
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q : out STD_LOGIC_VECTOR
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);
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end component;
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signal rst_S : std_logic := '1';
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signal rst_delay_s : std_logic := '1';
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signal rst_change_S : std_logic := '1';
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signal rst_sum_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal data_in_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal program_S : std_logic := '0';
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signal del1_data_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal del2_data_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal win_diff_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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-- signal del_win_diff_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal sub_result_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal change_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal wide_change_S : std_logic_vector(M_WIDTH - 1 downto 0) := (others => '0');
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signal add_result_S : std_logic_vector(M_WIDTH - 1 downto 0) := (others => '0');
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signal decay_corr_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal mult_sum_S : std_logic_vector(M_WIDTH - 1 downto 0) := (others => '0');
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signal factor_S : std_logic_vector(M_WIDTH - 1 downto 0) := conv_std_logic_vector(37213, M_WIDTH);
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signal product36 : std_logic_vector(35 downto 0) := (others => '0');
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signal data_out_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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-----------------------------------------------------------------------
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begin
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rst_S <= rst;
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clk_S <= clk;
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enable_S <= enable;
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data_in_S <= data_in;
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data_out <= data_out_S;
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program_proc : process (clk_S, rst_S)
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begin
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if rising_edge(clk_S) then
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program_S <= program;
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if (rst_S = '1') then
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factor_S <= (others => '0');
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else
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program_S <= program;
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if (program = '1') and (program_S = '0') then
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factor_S <= conv_std_logic_vector(conv_integer(correction_in), factor_S'length);
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end if;
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end if;
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end if;
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end process;
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diff_proc : process(clk_S, rst_delay_s)
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begin
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if rising_edge(clk_S) then
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if (rst_S = '1') then
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del1_data_S <= (others => '0');
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del2_data_S <= (others => '0');
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-- win_diff_S <= (others => '0');
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else
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del1_data_S <= data_in_S;
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del2_data_S <= del1_data_S;
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-- win_diff_S <= conv_std_logic_vector((conv_integer(signed(data_in_S)) - conv_integer(signed(del2_data_S))), WIDTH);
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-- del_win_diff_S <= win_diff_S;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------------------------------
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-- below is the 2-stage moving average
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-------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------------------------------
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reset_proc : process(clk_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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rst_delay_s <= '1';
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rst_change_S <= '1';
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rst_sum_S <= '1';
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else
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rst_delay_s <= rst_S;
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rst_change_S <= rst_delay_s;
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rst_sum_S <= rst_change_S;
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end if;
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end if;
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end process;
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-- SUB = (a - b) !!
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sub_Msum : SISO_sub_a
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GENERIC MAP(--WIDTH =>WIDTH,
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A_MINUS_B => true)
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PORT MAP(dataa => data_in_S,
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datab => del2_data_S,
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result => sub_result_S
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);
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change_reg : dff_re
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PORT MAP(rst => rst_change_S,
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clk => clk_S,
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enable => enable_S,
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d => sub_result_S,
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q => change_S
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);
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delay_reg : dff_re -- saving code (and resources ??)
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PORT MAP(rst => rst_change_S,
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clk => clk_S,
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enable => enable_S,
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d => change_S,
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q => win_diff_S
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);
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wide_change_S <= conv_std_logic_vector(conv_integer(change_S), M_WIDTH);
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add_Msum : SISO_add_a
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-- GENERIC MAP (WIDTH => M_WIDTH)
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PORT MAP(dataa => wide_change_S,
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datab => mult_sum_S,
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result => add_result_S
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);
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msum_reg : dff_re
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PORT MAP(rst => rst_sum_S,
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clk => clk_S,
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enable => enable_S,
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d => add_result_S,
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q => mult_sum_S
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);
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-- NOTE !! below product is effectively divided by 4
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decay_corr_S(16 downto 0) <= product36(33 downto 17);
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-- tau = 3.2ns ! dus ln2/(3.2E-9 * 50E6) = 0.693 / 0.16 = 4.332, MWD_size=2 => MWD_PWR=1
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decay_correction_proc : process(clk_S, rst_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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product36 <= (others => '0');
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data_out_S <= (others => '0');
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else
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if (enable_S = '1') then
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-- NOTE !! below factor and product are effectively divided by 4, to be restored in decay_correction
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product36 <= mult_sum_S * ('0' & '0' & factor_S(17 downto 2));
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-- data_out_S <= win_diff_S + decay_corr_S;
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data_out_S <= conv_std_logic_vector((conv_integer(signed(win_diff_S)) + conv_integer(signed(decay_corr_S))), WIDTH);
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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