1 |
2 |
panda_emc |
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2 |
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NET "system_adc_clk_p" TNM_NET = "system_adc_clk_p";
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3 |
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TIMESPEC "TS_system_adc_clk_p" = PERIOD "system_adc_clk_p" 10.0 ns HIGH 50 %;
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4 |
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5 |
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NET "adc1_clk" TNM_NET = "adc1_clk";
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6 |
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TIMESPEC "TS_adc1_dco_p" = PERIOD "adc1_clk" 10 ns HIGH 50 %;
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7 |
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8 |
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9 |
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NET "adc2_clk" TNM_NET = "adc2_clk";
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10 |
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TIMESPEC "TS_adc2_dco_p" = PERIOD "adc2_clk" 10 ns HIGH 50 %;
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11 |
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12 |
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NET "system_clk_ibufg" TNM_NET = "system_clk_ibufg";
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13 |
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TIMESPEC "TS_system_clk_ibufg" = PERIOD "system_clk_ibufg" 9.0 ns HIGH 50 %;
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14 |
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15 |
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NET "system_clk_p" TNM_NET = "system_clk_p";
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16 |
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NET "adc2_dco_p" TNM_NET = "adc2_dco_p";
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17 |
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NET "adc1_dco_p" TNM_NET = "adc1_dco_p";
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18 |
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NET "clk90_int" TNM_NET = "TN_ddr_clock90";
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19 |
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NET "clk_int" TNM_NET = "TN_ddr_clock";
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20 |
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NET "sys_clk_100" TNM_NET = "TN_sys_100_clock";
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21 |
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TIMESPEC "TS_sys_100_clock_to_ddr_clock90" = FROM "TN_sys_100_clock" TO "TN_ddr_clock90" 10 ns;
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22 |
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TIMESPEC "TS_ddr_clock90_to_sys_100_clock" = FROM "TN_ddr_clock90" TO "TN_sys_100_clock" 10 ns;
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23 |
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TIMESPEC "TS_sys_100_clock_to_ddr_clock" = FROM "TN_sys_100_clock" TO "TN_ddr_clock" 10 ns;
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24 |
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TIMESPEC "TS_ddr_clock_to_sys_100_clock" = FROM "TN_ddr_clock" TO "TN_sys_100_clock" 10 ns;
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25 |
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26 |
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NET "adc1_clk" TNM_NET = "TN_adc1_clk";
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27 |
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TIMESPEC "TS_adc1_clk_to_sys_100_clock" = FROM "TN_adc1_clk" TO "TN_sys_100_clock" 10 ns;
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28 |
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TIMESPEC "TS_sys_100_clock_to_adc1_clk" = FROM "TN_sys_100_clock" TO "TN_adc1_clk" 10 ns;
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29 |
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30 |
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#PL
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31 |
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#NET "adc2_clk" TNM_NET = "TN_adc2_clk";
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32 |
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#TIMESPEC "TS_adc2_clk_to_sys_100_clock" = FROM "TN_adc2_clk" TO "TN_sys_100_clock" 10 ns;
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33 |
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#TIMESPEC "TS_sys_100_clock_to_adc2_clk" = FROM "TN_sys_100_clock" TO "TN_adc2_clk" 10 ns;
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34 |
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#PL
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35 |
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36 |
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TIMEGRP "timegr_dqs" = PADS( "ddr1_dqs<0>" "ddr1_dqs<1>" );
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37 |
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TIMEGRP "timegr_dq" = PADS( "ddr1_dq<0>" "ddr1_dq<1>" "ddr1_dq<2>" "ddr1_dq<3>" "ddr1_dq<4>" "ddr1_dq<5>" "ddr1_dq<6>" "ddr1_dq<7>" "ddr1_dq<8>" "ddr1_dq<9>" "ddr1_dq<10>" "ddr1_dq<11>" "ddr1_dq<12>" "ddr1_dq<13>" "ddr1_dq<14>" "ddr1_dq<15>" );
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38 |
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39 |
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40 |
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NET "system_adc_clk" MAXDELAY = 1000ps ;
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41 |
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NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in" MAXDELAY = 2000ps ; #600ps
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42 |
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NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in" MAXDELAY = 2000ps ; #600ps
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43 |
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NET "ram2_ddr2_dq_in_rising*" MAXDELAY = 600ps ;
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44 |
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NET "ram2_ddr2_dq_in_falling*" MAXDELAY = 600ps ;
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45 |
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46 |
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47 |
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NET "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/din_delay" MAXDELAY = 400ps ;
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48 |
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NET "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
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49 |
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NET "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/din_delay" MAXDELAY = 400ps ;
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50 |
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NET "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
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51 |
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NET "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/dout0" MAXDELAY = 400ps ;
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52 |
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NET "ram2_ddr2_data_path/fifo*_wr_en" MAXDELAY = 1100ps ;
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53 |
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NET "ram2_ddr2_data_path/fifo*_wr_addr*" MAXDELAY = 2000ps ;
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54 |
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NET "ram2_ddr2_data_path/fifo*_rd_addr*" MAXDELAY = 2000ps ;
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55 |
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NET "ram2_ddr2_data_path/data_read0/fifo*rd_addr_r*" MAXDELAY = 2000ps ;
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56 |
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NET "ram2_ddr2_data_path/data_read0/fifo_*_data_out*" MAXDELAY = 2500ps ;
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57 |
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NET "ram2_ddr2_data_path/reset_r*" MAXDELAY = 1500ps ;
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58 |
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NET "ram2_controller/rst_dqs_div_r*" MAXDELAY = 800ps ;
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59 |
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NET "ram2_ddr2_rst_dqs_div_int*" MAXDELAY = 800ps ;
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60 |
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NET "ram2_controller/dqs_reset*" MAXDELAY = 1800ps ;
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61 |
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NET "ram2_ddr2_rst_dqs_div" MAXDELAY = 800ps ;
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62 |
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63 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit0" LOC = "SLICE_X78Y78";
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64 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit0" LOC = "SLICE_X76Y78";
|
65 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit1" LOC = "SLICE_X78Y79";
|
66 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit1" LOC = "SLICE_X76Y79";
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67 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit2" LOC = "SLICE_X78Y80";
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68 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit2" LOC = "SLICE_X76Y80";
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69 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit3" LOC = "SLICE_X78Y81";
|
70 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit3" LOC = "SLICE_X76Y81";
|
71 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit4" LOC = "SLICE_X78Y82";
|
72 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit4" LOC = "SLICE_X76Y82";
|
73 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit5" LOC = "SLICE_X78Y83";
|
74 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit5" LOC = "SLICE_X76Y83";
|
75 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit6" LOC = "SLICE_X78Y86";
|
76 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit6" LOC = "SLICE_X76Y86";
|
77 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit7" LOC = "SLICE_X78Y87";
|
78 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit7" LOC = "SLICE_X76Y87";
|
79 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = "SLICE_X79Y86";
|
80 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = "SLICE_X79Y86";
|
81 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = "SLICE_X79Y87";
|
82 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = "SLICE_X79Y87";
|
83 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/delay_ff" LOC = "SLICE_X77Y78";
|
84 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = "SLICE_X77Y86";
|
85 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = "SLICE_X77Y86";
|
86 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = "SLICE_X77Y87";
|
87 |
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = "SLICE_X77Y87";
|
88 |
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y78";
|
89 |
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|
90 |
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|
91 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit8" LOC = "SLICE_X78Y54";
|
92 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit8" LOC = "SLICE_X76Y54";
|
93 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit9" LOC = "SLICE_X78Y52";
|
94 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit9" LOC = "SLICE_X76Y52";
|
95 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit10" LOC = "SLICE_X78Y56";
|
96 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit10" LOC = "SLICE_X76Y56";
|
97 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit11" LOC = "SLICE_X78Y55";
|
98 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit11" LOC = "SLICE_X76Y55";
|
99 |
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit12" LOC = "SLICE_X78Y68";
|
100 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit12" LOC = "SLICE_X76Y68";
|
101 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit13" LOC = "SLICE_X78Y69";
|
102 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit13" LOC = "SLICE_X76Y69";
|
103 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit14" LOC = "SLICE_X78Y72";
|
104 |
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit14" LOC = "SLICE_X76Y72";
|
105 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo0_bit15" LOC = "SLICE_X78Y73";
|
106 |
|
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INST "ram2_ddr2_data_path/data_read0/fifo1_bit15" LOC = "SLICE_X76Y73";
|
107 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = "SLICE_X79Y72";
|
108 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = "SLICE_X79Y72";
|
109 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = "SLICE_X79Y73";
|
110 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = "SLICE_X79Y73";
|
111 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/delay_ff" LOC = "SLICE_X77Y53";
|
112 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = "SLICE_X77Y72";
|
113 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = "SLICE_X77Y72";
|
114 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = "SLICE_X77Y73";
|
115 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = "SLICE_X77Y73";
|
116 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y53";
|
117 |
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|
118 |
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|
119 |
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay1" LOC = SLICE_X79Y85 ;
|
120 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay2" LOC = SLICE_X79Y85 ;
|
121 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay3" LOC = SLICE_X79Y84 ;
|
122 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay4" LOC = SLICE_X79Y84 ;
|
123 |
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|
124 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay1" LOC = SLICE_X79Y69 ;
|
125 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay2" LOC = SLICE_X79Y69 ; # XXY42
|
126 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay3" LOC = SLICE_X79Y68 ;
|
127 |
|
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INST "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay4" LOC = SLICE_X79Y68 ; # XXY42
|
128 |
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|
129 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay1" LOC = SLICE_X74Y85 ;
|
130 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay2" LOC = SLICE_X74Y85 ;
|
131 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay3" LOC = SLICE_X74Y84 ;
|
132 |
|
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INST "ram2_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay4" LOC = SLICE_X74Y84 ;
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133 |
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134 |
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135 |
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136 |
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137 |
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#--******************************************************************************************************+
|
138 |
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|
139 |
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NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in" MAXDELAY = 2000ps ; # 600ps
|
140 |
|
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NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in" MAXDELAY = 2000ps ; # 600ps
|
141 |
|
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NET "ram1_ddr2_dq_in_rising*" MAXDELAY = 600ps ;
|
142 |
|
|
NET "ram1_ddr2_dq_in_falling*" MAXDELAY = 600ps ;
|
143 |
|
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#NET "ram1_ddr2_dqs_int_delay_in*" MAXDELAY = 600ps
|
144 |
|
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NET "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/din_delay" MAXDELAY = 400ps ;
|
145 |
|
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NET "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
|
146 |
|
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NET "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/din_delay" MAXDELAY = 400ps ;
|
147 |
|
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NET "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/din_delay_1" MAXDELAY = 400ps ;
|
148 |
|
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NET "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/dout0" MAXDELAY = 400ps ;
|
149 |
|
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NET "ram1_ddr2_data_path/fifo*_wr_en" MAXDELAY = 1000ps ;
|
150 |
|
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NET "ram1_ddr2_data_path/fifo*_wr_addr*" MAXDELAY = 2350ps ;
|
151 |
|
|
NET "ram1_ddr2_data_path/fifo*_rd_addr*" MAXDELAY = 2350ps ;
|
152 |
|
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NET "ram1_ddr2_data_path/data_read0/fifo*rd_addr_r*" MAXDELAY = 2350ps ;
|
153 |
|
|
NET "ram1_ddr2_data_path/data_read0/fifo_*_data_out*" MAXDELAY = 2500ps ;
|
154 |
|
|
NET "ram1_ddr2_data_path/reset_r*" MAXDELAY = 1500ps ;
|
155 |
|
|
NET "ram1_controller/rst_dqs_div_r*" MAXDELAY = 800ps ;
|
156 |
|
|
NET "ram1_ddr2_rst_dqs_div_int*" MAXDELAY = 800ps ;
|
157 |
|
|
NET "ram1_controller/dqs_reset*" MAXDELAY = 1800ps ;
|
158 |
|
|
NET "ram1_ddr2_rst_dqs_div" MAXDELAY = 800ps ;
|
159 |
|
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|
160 |
|
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INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay1" LOC = SLICE_X79Y11 ;
|
161 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay2" LOC = SLICE_X79Y11 ;
|
162 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay3" LOC = SLICE_X79Y10 ;
|
163 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_lut_delay4" LOC = SLICE_X79Y10 ;
|
164 |
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|
165 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay1" LOC = SLICE_X79Y27 ;
|
166 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay2" LOC = SLICE_X79Y27 ;
|
167 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay3" LOC = SLICE_X79Y26 ;
|
168 |
|
|
INST "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_lut_delay4" LOC = SLICE_X79Y26 ;
|
169 |
|
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|
170 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay1" LOC = SLICE_X74Y25 ;
|
171 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay2" LOC = SLICE_X74Y25 ;
|
172 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay3" LOC = SLICE_X74Y24 ;
|
173 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/rst_dqs_div_lut_delay4" LOC = SLICE_X74Y24 ;
|
174 |
|
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|
175 |
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|
176 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit0" LOC = "SLICE_X78Y12";
|
177 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit0" LOC = "SLICE_X76Y12";
|
178 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit1" LOC = "SLICE_X78Y13";
|
179 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit1" LOC = "SLICE_X76Y13";
|
180 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit2" LOC = "SLICE_X78Y14";
|
181 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit2" LOC = "SLICE_X76Y14";
|
182 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit3" LOC = "SLICE_X78Y15";
|
183 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit3" LOC = "SLICE_X76Y15";
|
184 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit4" LOC = "SLICE_X78Y16";
|
185 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit4" LOC = "SLICE_X76Y16";
|
186 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit5" LOC = "SLICE_X78Y17";
|
187 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit5" LOC = "SLICE_X76Y17";
|
188 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit6" LOC = "SLICE_X78Y18";
|
189 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit6" LOC = "SLICE_X76Y18";
|
190 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit7" LOC = "SLICE_X78Y19";
|
191 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit7" LOC = "SLICE_X76Y19";
|
192 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = "SLICE_X79Y18";
|
193 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = "SLICE_X79Y18";
|
194 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = "SLICE_X79Y19";
|
195 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = "SLICE_X79Y19";
|
196 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_00_wr_en_inst/delay_ff" LOC = "SLICE_X77Y12";
|
197 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = "SLICE_X77Y18";
|
198 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = "SLICE_X77Y18";
|
199 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = "SLICE_X77Y19";
|
200 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = "SLICE_X77Y19";
|
201 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_01_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y12";
|
202 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit8" LOC = "SLICE_X78Y26";
|
203 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit8" LOC = "SLICE_X76Y26";
|
204 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit9" LOC = "SLICE_X78Y27";
|
205 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit9" LOC = "SLICE_X76Y27";
|
206 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit10" LOC = "SLICE_X78Y40";
|
207 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit10" LOC = "SLICE_X76Y40";
|
208 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit11" LOC = "SLICE_X78Y41";
|
209 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit11" LOC = "SLICE_X76Y41";
|
210 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit12" LOC = "SLICE_X78Y42";
|
211 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit12" LOC = "SLICE_X76Y42";
|
212 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit13" LOC = "SLICE_X78Y43";
|
213 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit13" LOC = "SLICE_X76Y43";
|
214 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit14" LOC = "SLICE_X78Y48";
|
215 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit14" LOC = "SLICE_X76Y48";
|
216 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo0_bit15" LOC = "SLICE_X78Y49";
|
217 |
|
|
INST "ram1_ddr2_data_path/data_read0/fifo1_bit15" LOC = "SLICE_X76Y49";
|
218 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = "SLICE_X79Y48";
|
219 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = "SLICE_X79Y48";
|
220 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = "SLICE_X79Y49";
|
221 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = "SLICE_X79Y49";
|
222 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_10_wr_en_inst/delay_ff" LOC = "SLICE_X77Y26";
|
223 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = "SLICE_X77Y48";
|
224 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = "SLICE_X77Y48";
|
225 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = "SLICE_X77Y49";
|
226 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = "SLICE_X77Y49";
|
227 |
|
|
INST "ram1_ddr2_data_path/data_read_controller0/fifo_11_wr_en_inst/delay_ff_1" LOC = "SLICE_X79Y26";
|
228 |
|
|
|
229 |
|
|
|
230 |
|
|
#PACE: Start of Constraints generated by PACE
|
231 |
|
|
|
232 |
|
|
#PACE: Start of PACE I/O Pin Assignments
|
233 |
|
|
NET "adc1_clk_out_n" LOC = "M6" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
|
234 |
|
|
NET "adc1_clk_out_p" LOC = "M5" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
|
235 |
|
|
NET "adc1_dco_n" LOC = "AA11" | IOSTANDARD = LVDS_25 ;
|
236 |
|
|
NET "adc1_dco_p" LOC = "Y11" | IOSTANDARD = LVDS_25 ;
|
237 |
|
|
NET "adc1_din_n<0>" LOC = "Y3" | IOSTANDARD = LVDS_25 ;
|
238 |
|
|
NET "adc1_din_n<10>" LOC = "R5" | IOSTANDARD = LVDS_25 ;
|
239 |
|
|
NET "adc1_din_n<11>" LOC = "P2" | IOSTANDARD = LVDS_25 ;
|
240 |
|
|
NET "adc1_din_n<12>" LOC = "P5" | IOSTANDARD = LVDS_25 ;
|
241 |
|
|
NET "adc1_din_n<13>" LOC = "N2" | IOSTANDARD = LVDS_25 ;
|
242 |
|
|
NET "adc1_din_n<14>" LOC = "M2" | IOSTANDARD = LVDS_25 ;
|
243 |
|
|
NET "adc1_din_n<15>" LOC = "N6" | IOSTANDARD = LVDS_25 ;
|
244 |
|
|
NET "adc1_din_n<1>" LOC = "W4" | IOSTANDARD = LVDS_25 ;
|
245 |
|
|
NET "adc1_din_n<2>" LOC = "W2" | IOSTANDARD = LVDS_25 ;
|
246 |
|
|
NET "adc1_din_n<3>" LOC = "V2" | IOSTANDARD = LVDS_25 ;
|
247 |
|
|
NET "adc1_din_n<4>" LOC = "V4" | IOSTANDARD = LVDS_25 ;
|
248 |
|
|
NET "adc1_din_n<5>" LOC = "T2" | IOSTANDARD = LVDS_25 ;
|
249 |
|
|
NET "adc1_din_n<6>" LOC = "V5" | IOSTANDARD = LVDS_25 ;
|
250 |
|
|
NET "adc1_din_n<7>" LOC = "U4" | IOSTANDARD = LVDS_25 ;
|
251 |
|
|
NET "adc1_din_n<8>" LOC = "T6" | IOSTANDARD = LVDS_25 ;
|
252 |
|
|
NET "adc1_din_n<9>" LOC = "R2" | IOSTANDARD = LVDS_25 ;
|
253 |
|
|
NET "adc1_din_p<0>" LOC = "Y2" | IOSTANDARD = LVDS_25 ;
|
254 |
|
|
NET "adc1_din_p<10>" LOC = "P6" | IOSTANDARD = LVDS_25 ;
|
255 |
|
|
NET "adc1_din_p<11>" LOC = "P1" | IOSTANDARD = LVDS_25 ;
|
256 |
|
|
NET "adc1_din_p<12>" LOC = "P4" | IOSTANDARD = LVDS_25 ;
|
257 |
|
|
NET "adc1_din_p<13>" LOC = "N1" | IOSTANDARD = LVDS_25 ;
|
258 |
|
|
NET "adc1_din_p<14>" LOC = "M1" | IOSTANDARD = LVDS_25 ;
|
259 |
|
|
NET "adc1_din_p<15>" LOC = "N5" | IOSTANDARD = LVDS_25 ;
|
260 |
|
|
NET "adc1_din_p<1>" LOC = "W3" | IOSTANDARD = LVDS_25 ;
|
261 |
|
|
NET "adc1_din_p<2>" LOC = "W1" | IOSTANDARD = LVDS_25 ;
|
262 |
|
|
NET "adc1_din_p<3>" LOC = "V1" | IOSTANDARD = LVDS_25 ;
|
263 |
|
|
NET "adc1_din_p<4>" LOC = "V3" | IOSTANDARD = LVDS_25 ;
|
264 |
|
|
NET "adc1_din_p<5>" LOC = "T1" | IOSTANDARD = LVDS_25 ;
|
265 |
|
|
NET "adc1_din_p<6>" LOC = "U5" | IOSTANDARD = LVDS_25 ;
|
266 |
|
|
NET "adc1_din_p<7>" LOC = "T4" | IOSTANDARD = LVDS_25 ;
|
267 |
|
|
NET "adc1_din_p<8>" LOC = "T5" | IOSTANDARD = LVDS_25 ;
|
268 |
|
|
NET "adc1_din_p<9>" LOC = "R1" | IOSTANDARD = LVDS_25 ;
|
269 |
|
|
NET "adc2_clk_out_n" LOC = "C3" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
|
270 |
|
|
NET "adc2_clk_out_p" LOC = "C4" | IOSTANDARD = LVDS_25 | SLEW = FAST ;
|
271 |
|
|
NET "adc2_dco_n" LOC = "B11" | IOSTANDARD = LVDS_25 ;
|
272 |
|
|
NET "adc2_dco_p" LOC = "A11" | IOSTANDARD = LVDS_25 ;
|
273 |
|
|
NET "adc2_din_n<0>" LOC = "L1" | IOSTANDARD = LVDS_25 ;
|
274 |
|
|
NET "adc2_din_n<10>" LOC = "G1" | IOSTANDARD = LVDS_25 ;
|
275 |
|
|
NET "adc2_din_n<11>" LOC = "G3" | IOSTANDARD = LVDS_25 ;
|
276 |
|
|
NET "adc2_din_n<12>" LOC = "F2" | IOSTANDARD = LVDS_25 ;
|
277 |
|
|
NET "adc2_din_n<13>" LOC = "E1" | IOSTANDARD = LVDS_25 ;
|
278 |
|
|
NET "adc2_din_n<14>" LOC = "D1" | IOSTANDARD = LVDS_25 ;
|
279 |
|
|
NET "adc2_din_n<15>" LOC = "D3" | IOSTANDARD = LVDS_25 ;
|
280 |
|
|
NET "adc2_din_n<1>" LOC = "K1" | IOSTANDARD = LVDS_25 ;
|
281 |
|
|
NET "adc2_din_n<2>" LOC = "L3" | IOSTANDARD = LVDS_25 ;
|
282 |
|
|
NET "adc2_din_n<3>" LOC = "K3" | IOSTANDARD = LVDS_25 ;
|
283 |
|
|
NET "adc2_din_n<4>" LOC = "K5" | IOSTANDARD = LVDS_25 ;
|
284 |
|
|
NET "adc2_din_n<5>" LOC = "J1" | IOSTANDARD = LVDS_25 ;
|
285 |
|
|
NET "adc2_din_n<6>" LOC = "J4" | IOSTANDARD = LVDS_25 ;
|
286 |
|
|
NET "adc2_din_n<7>" LOC = "J5" | IOSTANDARD = LVDS_25 ;
|
287 |
|
|
NET "adc2_din_n<8>" LOC = "H1" | IOSTANDARD = LVDS_25 ;
|
288 |
|
|
NET "adc2_din_n<9>" LOC = "H5" | IOSTANDARD = LVDS_25 ;
|
289 |
|
|
NET "adc2_din_p<0>" LOC = "L2" | IOSTANDARD = LVDS_25 ;
|
290 |
|
|
NET "adc2_din_p<10>" LOC = "G2" | IOSTANDARD = LVDS_25 ;
|
291 |
|
|
NET "adc2_din_p<11>" LOC = "G4" | IOSTANDARD = LVDS_25 ;
|
292 |
|
|
NET "adc2_din_p<12>" LOC = "F3" | IOSTANDARD = LVDS_25 ;
|
293 |
|
|
NET "adc2_din_p<13>" LOC = "E2" | IOSTANDARD = LVDS_25 ;
|
294 |
|
|
NET "adc2_din_p<14>" LOC = "C1" | IOSTANDARD = LVDS_25 ;
|
295 |
|
|
NET "adc2_din_p<15>" LOC = "D2" | IOSTANDARD = LVDS_25 ;
|
296 |
|
|
NET "adc2_din_p<1>" LOC = "K2" | IOSTANDARD = LVDS_25 ;
|
297 |
|
|
NET "adc2_din_p<2>" LOC = "L4" | IOSTANDARD = LVDS_25 ;
|
298 |
|
|
NET "adc2_din_p<3>" LOC = "K4" | IOSTANDARD = LVDS_25 ;
|
299 |
|
|
NET "adc2_din_p<4>" LOC = "K6" | IOSTANDARD = LVDS_25 ;
|
300 |
|
|
NET "adc2_din_p<5>" LOC = "J2" | IOSTANDARD = LVDS_25 ;
|
301 |
|
|
NET "adc2_din_p<6>" LOC = "H4" | IOSTANDARD = LVDS_25 ;
|
302 |
|
|
NET "adc2_din_p<7>" LOC = "J6" | IOSTANDARD = LVDS_25 ;
|
303 |
|
|
NET "adc2_din_p<8>" LOC = "H2" | IOSTANDARD = LVDS_25 ;
|
304 |
|
|
NET "adc2_din_p<9>" LOC = "G5" | IOSTANDARD = LVDS_25 ;
|
305 |
|
|
NET "ddr1_address<0>" LOC = "AB18" | IOSTANDARD = SSTL18_I ;
|
306 |
|
|
NET "ddr1_address<10>" LOC = "W17" | IOSTANDARD = SSTL18_I ;
|
307 |
|
|
NET "ddr1_address<11>" LOC = "AA15" | IOSTANDARD = SSTL18_I ;
|
308 |
|
|
NET "ddr1_address<12>" LOC = "V14" | IOSTANDARD = SSTL18_I ;
|
309 |
|
|
NET "ddr1_address<13>" LOC = "Y13" | IOSTANDARD = SSTL18_I ;
|
310 |
|
|
NET "ddr1_address<14>" LOC = "AA16" | IOSTANDARD = SSTL18_I ;
|
311 |
|
|
NET "ddr1_address<15>" LOC = "AB16" | IOSTANDARD = SSTL18_I ;
|
312 |
|
|
NET "ddr1_address<1>" LOC = "AA18" | IOSTANDARD = SSTL18_I ;
|
313 |
|
|
NET "ddr1_address<2>" LOC = "U17" | IOSTANDARD = SSTL18_I ;
|
314 |
|
|
NET "ddr1_address<3>" LOC = "V17" | IOSTANDARD = SSTL18_I ;
|
315 |
|
|
NET "ddr1_address<4>" LOC = "AA17" | IOSTANDARD = SSTL18_I ;
|
316 |
|
|
NET "ddr1_address<5>" LOC = "U16" | IOSTANDARD = SSTL18_I ;
|
317 |
|
|
NET "ddr1_address<6>" LOC = "Y17" | IOSTANDARD = SSTL18_I ;
|
318 |
|
|
NET "ddr1_address<7>" LOC = "W16" | IOSTANDARD = SSTL18_I ;
|
319 |
|
|
NET "ddr1_address<8>" LOC = "V16" | IOSTANDARD = SSTL18_I ;
|
320 |
|
|
NET "ddr1_address<9>" LOC = "AB15" | IOSTANDARD = SSTL18_I ;
|
321 |
|
|
NET "ddr1_ba2_reserve" LOC = "U14" | IOSTANDARD = SSTL18_I ;
|
322 |
|
|
NET "ddr1_ba<0>" LOC = "Y18" | IOSTANDARD = SSTL18_I ;
|
323 |
|
|
NET "ddr1_ba<1>" LOC = "W14" | IOSTANDARD = SSTL18_I ;
|
324 |
|
|
NET "ddr1_casb" LOC = "U13" | IOSTANDARD = SSTL18_I ;
|
325 |
|
|
NET "ddr1_cke" LOC = "V19" | IOSTANDARD = SSTL18_I ;
|
326 |
|
|
NET "ddr1_clk" LOC = "W22" | IOSTANDARD = SSTL18_I ;
|
327 |
|
|
NET "ddr1_clkb" LOC = "Y22" | IOSTANDARD = SSTL18_I ;
|
328 |
|
|
NET "ddr1_csb" LOC = "Y21" | IOSTANDARD = SSTL18_I ;
|
329 |
|
|
NET "ddr1_dm<0>" LOC = "U21" | IOSTANDARD = SSTL18_I ;
|
330 |
|
|
NET "ddr1_dm<1>" LOC = "N20" | IOSTANDARD = SSTL18_I ;
|
331 |
|
|
NET "ddr1_dq<0>" LOC = "W20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
332 |
|
|
NET "ddr1_dq<10>" LOC = "N21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
333 |
|
|
NET "ddr1_dq<11>" LOC = "N22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
334 |
|
|
NET "ddr1_dq<12>" LOC = "M17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
335 |
|
|
NET "ddr1_dq<13>" LOC = "M18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
336 |
|
|
NET "ddr1_dq<14>" LOC = "L21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
337 |
|
|
NET "ddr1_dq<15>" LOC = "M21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
338 |
|
|
NET "ddr1_dq<1>" LOC = "W21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
339 |
|
|
NET "ddr1_dq<2>" LOC = "V20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
340 |
|
|
NET "ddr1_dq<3>" LOC = "U19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
341 |
|
|
NET "ddr1_dq<4>" LOC = "V21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
342 |
|
|
NET "ddr1_dq<5>" LOC = "V22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
343 |
|
|
NET "ddr1_dq<6>" LOC = "U18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
344 |
|
|
NET "ddr1_dq<7>" LOC = "T17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
345 |
|
|
NET "ddr1_dq<8>" LOC = "T21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
346 |
|
|
NET "ddr1_dq<9>" LOC = "T22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
347 |
|
|
NET "ddr1_dqs<0>" LOC = "R18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
|
348 |
|
|
NET "ddr1_dqs<1>" LOC = "M20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
|
349 |
|
|
NET "ddr1_dqs_reserve<0>" LOC = "T18" | IOSTANDARD = SSTL18_I ;
|
350 |
|
|
NET "ddr1_dqs_reserve<1>" LOC = "M19" | IOSTANDARD = SSTL18_I ;
|
351 |
|
|
NET "ddr1_ODT0" LOC = "AA13" | IOSTANDARD = SSTL18_I ;
|
352 |
|
|
NET "ddr1_rasb" LOC = "V13" | IOSTANDARD = SSTL18_I ;
|
353 |
|
|
NET "ddr1_rst_dqs_div_iob" LOC = "W15" | IOSTANDARD = SSTL18_I ;
|
354 |
|
|
NET "ddr1_web" LOC = "W13" | IOSTANDARD = SSTL18_I ;
|
355 |
|
|
NET "ddr2_address<0>" LOC = "D18" | IOSTANDARD = SSTL18_I ;
|
356 |
|
|
NET "ddr2_address<10>" LOC = "E17" | IOSTANDARD = SSTL18_I ;
|
357 |
|
|
NET "ddr2_address<11>" LOC = "F17" | IOSTANDARD = SSTL18_I ;
|
358 |
|
|
NET "ddr2_address<12>" LOC = "A13" | IOSTANDARD = SSTL18_I ;
|
359 |
|
|
NET "ddr2_address<13>" LOC = "B14" | IOSTANDARD = SSTL18_I ;
|
360 |
|
|
NET "ddr2_address<14>" LOC = "A16" | IOSTANDARD = SSTL18_I ;
|
361 |
|
|
NET "ddr2_address<15>" LOC = "B16" | IOSTANDARD = SSTL18_I ;
|
362 |
|
|
NET "ddr2_address<1>" LOC = "D14" | IOSTANDARD = SSTL18_I ;
|
363 |
|
|
NET "ddr2_address<2>" LOC = "C18" | IOSTANDARD = SSTL18_I ;
|
364 |
|
|
NET "ddr2_address<3>" LOC = "E16" | IOSTANDARD = SSTL18_I ;
|
365 |
|
|
NET "ddr2_address<4>" LOC = "B18" | IOSTANDARD = SSTL18_I ;
|
366 |
|
|
NET "ddr2_address<5>" LOC = "F13" | IOSTANDARD = SSTL18_I ;
|
367 |
|
|
NET "ddr2_address<6>" LOC = "C17" | IOSTANDARD = SSTL18_I ;
|
368 |
|
|
NET "ddr2_address<7>" LOC = "E15" | IOSTANDARD = SSTL18_I ;
|
369 |
|
|
NET "ddr2_address<8>" LOC = "B17" | IOSTANDARD = SSTL18_I ;
|
370 |
|
|
NET "ddr2_address<9>" LOC = "A14" | IOSTANDARD = SSTL18_I ;
|
371 |
|
|
NET "ddr2_ba2_reserve" LOC = "E14" | IOSTANDARD = SSTL18_I ;
|
372 |
|
|
NET "ddr2_ba<0>" LOC = "B19" | IOSTANDARD = SSTL18_I ;
|
373 |
|
|
NET "ddr2_ba<1>" LOC = "D15" | IOSTANDARD = SSTL18_I ;
|
374 |
|
|
NET "ddr2_casb" LOC = "B13" | IOSTANDARD = SSTL18_I ;
|
375 |
|
|
NET "ddr2_cke" LOC = "F16" | IOSTANDARD = SSTL18_I ;
|
376 |
|
|
NET "ddr2_clk" LOC = "B15" | IOSTANDARD = SSTL18_I ;
|
377 |
|
|
NET "ddr2_clkb" LOC = "A15" | IOSTANDARD = SSTL18_I ;
|
378 |
|
|
NET "ddr2_csb" LOC = "C22" | IOSTANDARD = SSTL18_I ;
|
379 |
|
|
NET "ddr2_dm<0>" LOC = "D21" | IOSTANDARD = SSTL18_I ;
|
380 |
|
|
NET "ddr2_dm<1>" LOC = "G19" | IOSTANDARD = SSTL18_I ;
|
381 |
|
|
NET "ddr2_dq<0>" LOC = "E22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
382 |
|
|
NET "ddr2_dq<10>" LOC = "K20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
383 |
|
|
NET "ddr2_dq<11>" LOC = "K22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
384 |
|
|
NET "ddr2_dq<12>" LOC = "G22" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
385 |
|
|
NET "ddr2_dq<13>" LOC = "G21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
386 |
|
|
NET "ddr2_dq<14>" LOC = "F20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
387 |
|
|
NET "ddr2_dq<15>" LOC = "F21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
388 |
|
|
NET "ddr2_dq<1>" LOC = "E21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
389 |
|
|
NET "ddr2_dq<2>" LOC = "E20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
390 |
|
|
NET "ddr2_dq<3>" LOC = "E19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
391 |
|
|
NET "ddr2_dq<4>" LOC = "F18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
392 |
|
|
NET "ddr2_dq<5>" LOC = "E18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
393 |
|
|
NET "ddr2_dq<6>" LOC = "D20" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
394 |
|
|
NET "ddr2_dq<7>" LOC = "D19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
395 |
|
|
NET "ddr2_dq<8>" LOC = "K21" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
396 |
|
|
NET "ddr2_dq<9>" LOC = "L18" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE ;
|
397 |
|
|
NET "ddr2_dqs<0>" LOC = "G17" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
|
398 |
|
|
NET "ddr2_dqs<1>" LOC = "L19" | IOSTANDARD = SSTL18_I | IOBDELAY = NONE | PULLDOWN ;
|
399 |
|
|
NET "ddr2_dqs_reserve<0>" LOC = "G18" | IOSTANDARD = SSTL18_I ;
|
400 |
|
|
NET "ddr2_dqs_reserve<1>" LOC = "L20" | IOSTANDARD = SSTL18_I ;
|
401 |
|
|
NET "ddr2_ODT0" LOC = "C13" | IOSTANDARD = SSTL18_I ;
|
402 |
|
|
NET "ddr2_rasb" LOC = "E12" | IOSTANDARD = SSTL18_I ;
|
403 |
|
|
NET "ddr2_rst_dqs_div_iob" LOC = "D13" | IOSTANDARD = SSTL18_I ;
|
404 |
|
|
NET "ddr2_web" LOC = "D17" | IOSTANDARD = SSTL18_I ;
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
NET "FPGA_ADC12_BUSY_L" LOC = "AB10" | SLEW = FAST ;
|
408 |
|
|
NET "FPGA_ADC12_EVENT_END_L" LOC = "AA10" | SLEW = FAST ;
|
409 |
|
|
NET "FPGA_ADC1_TRIGGER_L" LOC = "AA8" | SLEW = FAST ;
|
410 |
|
|
NET "FPGA_ADC2_TRIGGER_L" LOC = "Y10" | SLEW = FAST ;
|
411 |
|
|
NET "FPGA_ADC_B1_SAMPLE_ENABLED_L" LOC = "V7" | PULLUP ; # prot5
|
412 |
|
|
NET "FPGA_ADC_B2_SAMPLE_ENABLED_L" LOC = "V8" | PULLUP ; # prot6
|
413 |
|
|
NET "FPGA_ADC_SAMPLE_START_L" LOC = "V9" | PULLUP ; # prot7
|
414 |
|
|
NET "FPGA_ADC_SAMPLE_STOP_L" LOC = "V10" | PULLUP ; # prot8 MCA NOT_FIRST_SCAN Flag
|
415 |
|
|
NET "FPGA_ADC_SAMPLE_LOGIC_RESET_L" LOC = "W8" | PULLUP ;
|
416 |
|
|
|
417 |
|
|
NET "FPGA_ADC_TIMESTAMP_CLR_L" LOC = "W6" ; # prot11
|
418 |
|
|
NET "FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L" LOC = "Y6" ; # prot15
|
419 |
|
|
NET "FPGA_LEMO_USER_IN_L" LOC = "W5" ; # prot10 wird als Veto genutzt
|
420 |
|
|
|
421 |
|
|
NET "FPGA_ADC_PROT13_L" LOC = "W9" | PULLUP ; # prot13 MCA LNE
|
422 |
|
|
NET "FPGA_ADC_PROT14_L" LOC = "W10" | PULLUP ; # prot14 MCA Mode Enable
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
NET "CON_WITH_ADC12_OUT1_L" LOC = "B7" ; # out irq to next upper
|
428 |
|
|
NET "CON_WITH_ADC12_IN1_L" LOC = "A7" ; # in irq from next upper
|
429 |
|
|
NET "CON_WITH_ADC12_OUT2_L" LOC = "E8" ;
|
430 |
|
|
NET "CON_WITH_ADC12_IN2_L" LOC = "D8" ;
|
431 |
|
|
|
432 |
|
|
NET "CON_WITH_ADC78_IN1_L" LOC = "AA4" ; # in irq from next lower
|
433 |
|
|
NET "CON_WITH_ADC78_OUT1_L" LOC = "AA5" ; # out irq to next lower
|
434 |
|
|
NET "CON_WITH_ADC78_IN2_L" LOC = "AB4" ;
|
435 |
|
|
NET "CON_WITH_ADC78_OUT2_L" LOC = "AB5" ;
|
436 |
|
|
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
NET "FPGA_ID_D0" LOC = "AB7" ;
|
440 |
|
|
NET "FPGA_ID_D1" LOC = "AA7" ;
|
441 |
|
|
|
442 |
|
|
|
443 |
|
|
NET "i_fpga_reset_l" LOC = "U6" | PULLUP ; # prot0
|
444 |
|
|
NET "i_fpga_key_reset_l" LOC = "Y5" | PULLUP ; # prot9
|
445 |
|
|
|
446 |
|
|
NET "i_fpga_sel_l" LOC = "AB8" | PULLUP;
|
447 |
|
|
NET "i_fpga_ds_l" LOC = "U7" | PULLUP; # prot1
|
448 |
|
|
NET "i_fpga_write_l" LOC = "U10"| PULLUP ; # prot2
|
449 |
|
|
NET "i_fpga_block_l" LOC = "U11" | PULLUP; # prot3
|
450 |
|
|
NET "wst_out_l_oreg" LOC = "V6" | SLEW = FAST | DRIVE = 12 ; # prot4
|
451 |
|
|
|
452 |
|
|
NET "io_fpga_ad<0>" LOC = "A10" | SLEW = FAST | DRIVE = 12 ;
|
453 |
|
|
NET "io_fpga_ad<10>" LOC = "B5" | SLEW = FAST | DRIVE = 12 ;
|
454 |
|
|
NET "io_fpga_ad<11>" LOC = "B4" | SLEW = FAST | DRIVE = 12 ;
|
455 |
|
|
NET "io_fpga_ad<12>" LOC = "C11" | SLEW = FAST | DRIVE = 12 ;
|
456 |
|
|
NET "io_fpga_ad<13>" LOC = "C10" | SLEW = FAST | DRIVE = 12 ;
|
457 |
|
|
NET "io_fpga_ad<14>" LOC = "C7" | SLEW = FAST | DRIVE = 12 ;
|
458 |
|
|
NET "io_fpga_ad<15>" LOC = "C6" | SLEW = FAST | DRIVE = 12 ;
|
459 |
|
|
NET "io_fpga_ad<16>" LOC = "C5" | SLEW = FAST | DRIVE = 12 ;
|
460 |
|
|
NET "io_fpga_ad<17>" LOC = "D11" | SLEW = FAST | DRIVE = 12 ;
|
461 |
|
|
NET "io_fpga_ad<18>" LOC = "D10" | SLEW = FAST | DRIVE = 12 ;
|
462 |
|
|
NET "io_fpga_ad<19>" LOC = "D9" | SLEW = FAST | DRIVE = 12 ;
|
463 |
|
|
NET "io_fpga_ad<1>" LOC = "A9" | SLEW = FAST | DRIVE = 12 ;
|
464 |
|
|
NET "io_fpga_ad<20>" LOC = "D7" | SLEW = FAST | DRIVE = 12 ;
|
465 |
|
|
NET "io_fpga_ad<21>" LOC = "D6" | SLEW = FAST | DRIVE = 12 ;
|
466 |
|
|
NET "io_fpga_ad<22>" LOC = "D5" | SLEW = FAST | DRIVE = 12 ;
|
467 |
|
|
NET "io_fpga_ad<23>" LOC = "E11" | SLEW = FAST | DRIVE = 12 ;
|
468 |
|
|
NET "io_fpga_ad<24>" LOC = "E10" | SLEW = FAST | DRIVE = 12 ;
|
469 |
|
|
NET "io_fpga_ad<25>" LOC = "E9" | SLEW = FAST | DRIVE = 12 ;
|
470 |
|
|
NET "io_fpga_ad<26>" LOC = "E7" | SLEW = FAST | DRIVE = 12 ;
|
471 |
|
|
NET "io_fpga_ad<27>" LOC = "E6" | SLEW = FAST | DRIVE = 12 ;
|
472 |
|
|
NET "io_fpga_ad<28>" LOC = "F11" | SLEW = FAST | DRIVE = 12 ;
|
473 |
|
|
NET "io_fpga_ad<29>" LOC = "F10" | SLEW = FAST | DRIVE = 12 ;
|
474 |
|
|
NET "io_fpga_ad<2>" LOC = "A8" | SLEW = FAST | DRIVE = 12 ;
|
475 |
|
|
NET "io_fpga_ad<30>" LOC = "F9" | SLEW = FAST | DRIVE = 12 ;
|
476 |
|
|
NET "io_fpga_ad<31>" LOC = "F7" | SLEW = FAST | DRIVE = 12 ;
|
477 |
|
|
NET "io_fpga_ad<3>" LOC = "A5" | SLEW = FAST | DRIVE = 12 ;
|
478 |
|
|
NET "io_fpga_ad<4>" LOC = "A4" | SLEW = FAST | DRIVE = 12 ;
|
479 |
|
|
NET "io_fpga_ad<5>" LOC = "A3" | SLEW = FAST | DRIVE = 12 ;
|
480 |
|
|
NET "io_fpga_ad<6>" LOC = "B10" | SLEW = FAST | DRIVE = 12 ;
|
481 |
|
|
NET "io_fpga_ad<7>" LOC = "B9" | SLEW = FAST | DRIVE = 12 ;
|
482 |
|
|
NET "io_fpga_ad<8>" LOC = "B8" | SLEW = FAST | DRIVE = 12 ;
|
483 |
|
|
NET "io_fpga_ad<9>" LOC = "B6" | SLEW = FAST | DRIVE = 12 ;
|
484 |
|
|
NET "system_adc_clk_n" LOC = "AA12" | IOSTANDARD = LVDS_25 ;
|
485 |
|
|
NET "system_adc_clk_p" LOC = "AB12" | IOSTANDARD = LVDS_25 ;
|
486 |
|
|
NET "system_clk_n" LOC = "B12" | IOSTANDARD = LVDS_25 ;
|
487 |
|
|
NET "system_clk_p" LOC = "C12" | IOSTANDARD = LVDS_25 ;
|
488 |
|
|
|
489 |
|
|
#PACE: Start of PACE Area Constraints
|
490 |
|
|
|
491 |
|
|
#PACE: Start of PACE Prohibit Constraints
|
492 |
|
|
|
493 |
|
|
#PACE: End of Constraints generated by PACE
|
494 |
|
|
// 06/06 @ 10:12:07
|
495 |
|
|
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in"
|
496 |
|
|
ROUTE="{3;1;3s1000fg456;4c3cc268!-1;78200;-43440;S!0;-159;0!1;-1632;"
|
497 |
|
|
"-10208!1;-33;1777!2;-2809;-11239!3;-12136;-612!4;1009;1447!5;10269;38891!"
|
498 |
|
|
"6;327;0;L!7;226;-50240!9;1713;-7143!9;1705;-7135!9;1713;-3767!9;1705;"
|
499 |
|
|
"-3759!9;1713;-143!9;1705;-135!9;1713;3233!9;1705;3241!10;120;-161;L!10;"
|
500 |
|
|
"120;159;L!11;128;-161;L!11;128;159;L!12;120;-161;L!12;120;159;L!13;128;"
|
501 |
|
|
"-161;L!13;128;159;L!14;120;-161;L!14;120;159;L!15;128;-161;L!15;128;159;L"
|
502 |
|
|
"!16;120;-161;L!16;120;159;L!17;128;-161;L!17;128;159;L!}";
|
503 |
|
|
NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in"
|
504 |
|
|
ROUTE="{3;1;3s1000fg456;ece908db!-1;78200;-6056;S!0;-159;0!1;-1724;-1736!"
|
505 |
|
|
"1;-33;1777!2;-3476;-11784!3;-12136;-612!4;256;-13936!5;9804;7968!6;1512;"
|
506 |
|
|
"-2648!7;677;1195!7;677;-39813!7;691;-19317!8;327;0;L!9;1727;-3527!9;1719;"
|
507 |
|
|
"-3519!9;1727;-7151!9;1719;-7143!10;1719;-143!10;1727;-151!11;1705;3241!"
|
508 |
|
|
"11;1713;6609!11;1705;6617!11;1713;3233!13;120;159;L!14;128;159;L!15;120;"
|
509 |
|
|
"-161;L!16;128;-161;L!17;128;-161;L!17;128;159;L!18;120;159;L!18;120;-161;"
|
510 |
|
|
"L!19;128;-161;L!19;128;159;L!20;120;-161;L!20;120;159;L!21;128;-161;L!21;"
|
511 |
|
|
"128;159;L!22;120;159;L!22;120;-161;L!}";
|
512 |
|
|
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs0_in"
|
513 |
|
|
ROUTE="{3;1;3s1000fg456;8e10cbae!-1;78200;48456;S!0;-159;0!1;-33;1777!2;"
|
514 |
|
|
"-1576;7344!2;-12136;-612!3;-2816;3676!4;9732;-53400!5;993;1459!6;749;"
|
515 |
|
|
"62563!7;327;0;L!8;1727;-7151!8;1719;-7143!8;1727;-3527!8;1719;-3519!8;"
|
516 |
|
|
"1727;-151!8;1719;-143!8;1727;6601!8;1719;6609!10;120;-161;L!10;120;159;L!"
|
517 |
|
|
"11;128;-161;L!11;128;159;L!12;120;-161;L!12;120;159;L!13;128;-161;L!13;"
|
518 |
|
|
"128;159;L!14;120;-161;L!14;120;159;L!15;128;-161;L!15;128;159;L!16;120;"
|
519 |
|
|
"159;L!16;120;-161;L!17;128;159;L!17;128;-161;L!}";
|
520 |
|
|
NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs1_in"
|
521 |
|
|
ROUTE="{3;1;3s1000fg456;99c8b0b4!-1;78200;4320;S!0;-159;0!1;-1692;1736!1;"
|
522 |
|
|
"-33;1777!2;-3438;11712!3;-12136;-612!4;216;13568!5;9780;-12736!6;1482;"
|
523 |
|
|
"4128!7;715;42147!7;701;21651!8;327;0;L!9;1713;-143!9;1705;-135!9;1713;"
|
524 |
|
|
"6609!9;1705;6617!10;1727;-6903!10;1719;-6895!10;1727;-151!10;1719;-143!"
|
525 |
|
|
"10;1719;-3519!10;1727;-3527!12;120;-161;L!12;120;159;L!13;128;-161;L!13;"
|
526 |
|
|
"128;159;L!14;120;159;L!14;120;-161;L!15;128;159;L!15;128;-161;L!16;120;"
|
527 |
|
|
"-161;L!17;128;-161;L!18;120;-161;L!19;128;-161;L!20;128;159;L!20;128;"
|
528 |
|
|
"-161;L!21;120;-161;L!21;120;159;L!}";
|
529 |
|
|
|
530 |
|
|
|
531 |
|
|
|
532 |
|
|
NET "ram2_ddr2_dq_in_falling<0>"
|
533 |
|
|
ROUTE="{3;1;3s1000fg456;91159d71!-1;78200;51496;S!0;-208;-1247!1;-4376;"
|
534 |
|
|
"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
|
535 |
|
|
NET "ram2_ddr2_dq_in_falling<1>"
|
536 |
|
|
ROUTE="{3;1;3s1000fg456;22d15618!-1;78200;51816;S!0;-200;-1575!1;-4416;"
|
537 |
|
|
"660!2;-2431;651!3;167;0;L!}";
|
538 |
|
|
|
539 |
|
|
|
540 |
|
|
NET "ram2_ddr2_dq_in_falling<2>"
|
541 |
|
|
ROUTE="{3;1;3s1000fg456;4df40e72!-1;78200;55120;S!0;-2043;-592!1;-6173;"
|
542 |
|
|
"-65!2;1169;369!3;167;0;L!}";
|
543 |
|
|
|
544 |
|
|
NET "ram2_ddr2_dq_in_falling<3>"
|
545 |
|
|
ROUTE="{3;1;3s1000fg456;40d24bd1!-1;78200;55440;S!0;-200;-1699!1;-4416;"
|
546 |
|
|
"784!2;-2431;651!3;167;0;L!}";
|
547 |
|
|
|
548 |
|
|
#NET "ram2_ddr2_dq_in_falling<4>"
|
549 |
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#ROUTE="{3;1;3s1000fg456;6cd94ec0!-1;78200;58496;S!0;-192;2113!1;-4408;"
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550 |
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#"-712!2;-2447;-665!3;0;-1024!4;167;0;L!}";
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551 |
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552 |
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NET "ram2_ddr2_dq_in_falling<5>"
|
553 |
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ROUTE="{3;1;3s1000fg456;7ec24a76!-1;78200;58816;S!0;-200;-1575!1;-4416;"
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554 |
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"660!2;-2431;651!3;167;0;L!}";
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555 |
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556 |
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NET "ram2_ddr2_dq_in_falling<6>"
|
557 |
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ROUTE="{3;1;3s1000fg456;d255f653!-1;78200;65568;S!0;-2043;-912!1;-6173;"
|
558 |
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"-65!2;1169;369!3;167;0;L!}";
|
559 |
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560 |
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NET "ram2_ddr2_dq_in_falling<7>"
|
561 |
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ROUTE="{3;1;3s1000fg456;7f3336aa!-1;78200;65248;S!0;-200;-1255!1;-4416;"
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562 |
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"660!2;-2431;651!3;167;0;L!}";
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563 |
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564 |
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NET "ram2_ddr2_dq_in_falling<8>"
|
565 |
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ROUTE="{3;1;3s1000fg456;7d207d2!-1;78200;11056;S!0;-200;-1575!1;-4416;"
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566 |
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"660!2;-2431;307!3;167;0;L!}";
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567 |
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568 |
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NET "ram2_ddr2_dq_in_falling<9>"
|
569 |
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ROUTE="{3;1;3s1000fg456;ba0282c2!-1;78200;7360;S!0;-200;-1255!1;-4416;"
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570 |
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"660!2;-2431;307!3;167;0;L!}";
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571 |
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572 |
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NET "ram2_ddr2_dq_in_falling<10>"
|
573 |
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ROUTE="{3;1;3s1000fg456;96c2c681!-1;78200;14112;S!0;-200;-1255!1;-4416;"
|
574 |
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"660!2;-2431;307!3;167;0;L!}";
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575 |
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|
576 |
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#NET "ram2_ddr2_dq_in_falling<11>"
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577 |
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#ROUTE="{3;1;3s1000fg456;e53c8fe0!-1;78200;10736;S!0;-2043;-592!1;-6173;"
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578 |
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#"-65!2;1169;713!3;167;0;L!}";
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579 |
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|
580 |
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NET "ram2_ddr2_dq_in_falling<12>"
|
581 |
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ROUTE="{3;1;3s1000fg456;4f0b6976!-1;78200;34616;S!0;-2043;-592!1;-6173;"
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582 |
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"-65!2;1169;369!3;167;0;L!}";
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583 |
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NET "ram2_ddr2_dq_in_falling<13>"
|
584 |
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ROUTE="{3;1;3s1000fg456;37c962ec!-1;78200;34936;S!0;-200;-1575!1;-4416;"
|
585 |
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"660!2;-2431;651!3;167;0;L!}";
|
586 |
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NET "ram2_ddr2_dq_in_falling<14>"
|
587 |
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ROUTE="{3;1;3s1000fg456;b6eccd07!-1;78200;41688;S!0;-2043;-912!1;-6173;"
|
588 |
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"-65!2;1169;369!3;167;0;L!}";
|
589 |
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NET "ram2_ddr2_dq_in_falling<15>"
|
590 |
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ROUTE="{3;1;3s1000fg456;9062d6b2!-1;78200;41368;S!0;-200;-1255!1;-4416;"
|
591 |
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"660!2;-2431;651!3;167;0;L!}";
|
592 |
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593 |
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NET "ram2_ddr2_dq_in_rising<0>"
|
594 |
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ROUTE="{3;1;3s1000fg456;4df40e72!-1;78200;51504;S!0;-2043;-600!1;-1548;"
|
595 |
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"304!2;167;0;L!}";
|
596 |
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NET "ram2_ddr2_dq_in_rising<1>"
|
597 |
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ROUTE="{3;1;3s1000fg456;40d24bd1!-1;78200;51824;S!0;-2067;-928!1;-1524;"
|
598 |
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"648!2;0;8!3;167;0;L!}";
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599 |
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600 |
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601 |
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NET "ram2_ddr2_dq_in_rising<2>"
|
602 |
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ROUTE="{3;1;3s1000fg456;a98db838!-1;78200;55128;S!0;-2067;-608!1;-1524;"
|
603 |
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"648!2;0;-336!3;167;0;L!}";
|
604 |
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NET "ram2_ddr2_dq_in_rising<3>"
|
605 |
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ROUTE="{3;1;3s1000fg456;d3a4e30c!-1;78200;55448;S!0;-1851;1744!1;1828;"
|
606 |
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"584!2;-1281;15!3;-3763;-2583!4;1476;-32!5;167;0;L!}";
|
607 |
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NET "ram2_ddr2_dq_in_rising<4>"
|
608 |
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ROUTE="{3;1;3s1000fg456;90aac99f!-1;78200;58504;S!0;-2043;-600!1;-1548;"
|
609 |
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"304!2;167;0;L!}";
|
610 |
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NET "ram2_ddr2_dq_in_rising<5>"
|
611 |
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ROUTE="{3;1;3s1000fg456;f933645c!-1;78200;58824;S!0;-2067;-928!1;-1524;"
|
612 |
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"648!2;0;8!3;167;0;L!}";
|
613 |
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NET "ram2_ddr2_dq_in_rising<6>"
|
614 |
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ROUTE="{3;1;3s1000fg456;ac374ae0!-1;78200;65576;S!0;-2067;-928!1;-1524;"
|
615 |
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"648!2;0;-336!3;167;0;L!}";
|
616 |
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NET "ram2_ddr2_dq_in_rising<7>"
|
617 |
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ROUTE="{3;1;3s1000fg456;cfb24ace!-1;78200;65256;S!0;-2059;1400!1;-1532;"
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618 |
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"-672!2;0;-680!3;167;0;L!}";
|
619 |
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NET "ram2_ddr2_dq_in_rising<8>"
|
620 |
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ROUTE="{3;1;3s1000fg456;ada80821!-1;78200;11064;S!0;-1851;1744!1;1828;"
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621 |
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"584!2;-1281;15!3;-3763;-2583!4;1476;-376!5;167;0;L!}";
|
622 |
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NET "ram2_ddr2_dq_in_rising<9>"
|
623 |
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ROUTE="{3;1;3s1000fg456;9d9bf507!-1;78200;7368;S!0;-2043;-600!1;-1548;"
|
624 |
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"304!2;167;0;L!}";
|
625 |
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NET "ram2_ddr2_dq_in_rising<10>"
|
626 |
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ROUTE="{3;1;3s1000fg456;c827908e!-1;78200;14120;S!0;-2043;-600!1;-1548;"
|
627 |
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"304!2;167;0;L!}";
|
628 |
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NET "ram2_ddr2_dq_in_rising<11>"
|
629 |
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ROUTE="{3;1;3s1000fg456;72420bcc!-1;78200;10744;S!0;-2067;-608!1;-1524;"
|
630 |
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"648!2;0;8!3;167;0;L!}";
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631 |
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NET "ram2_ddr2_dq_in_rising<12>"
|
632 |
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ROUTE="{3;1;3s1000fg456;a36c7604!-1;78200;34624;S!0;-2067;-608!1;-1524;"
|
633 |
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"648!2;0;-336!3;167;0;L!}";
|
634 |
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|
635 |
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#NET "ram2_ddr2_dq_in_rising<13>"
|
636 |
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#ROUTE="{3;1;3s1000fg456;de3b8a2a!-1;78200;34944;S!0;-2059;1080!1;-1532;"
|
637 |
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#"-672!2;0;-680!3;167;0;L!}";
|
638 |
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|
639 |
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NET "ram2_ddr2_dq_in_rising<14>"
|
640 |
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ROUTE="{3;1;3s1000fg456;55f2a395!-1;78200;41696;S!0;-2067;-928!1;-1524;"
|
641 |
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"648!2;0;-336!3;167;0;L!}";
|
642 |
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NET "ram2_ddr2_dq_in_rising<15>"
|
643 |
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ROUTE="{3;1;3s1000fg456;e86eaa1!-1;78200;41376;S!0;-2059;1400!1;-1532;"
|
644 |
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"-672!2;0;-680!3;167;0;L!}";
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645 |
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646 |
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647 |
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648 |
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649 |
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// 06/06 @ 10:52:30
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650 |
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NET "ram1_ddr2_dq_in_falling<0>"
|
651 |
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ROUTE="{3;1;3s1000fg456;fad98df6!-1;78200;-60904;S!0;-208;-1247!1;-4376;"
|
652 |
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"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
|
653 |
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|
654 |
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|
655 |
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NET "ram1_ddr2_dq_in_falling<1>"
|
656 |
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ROUTE="{3;1;3s1000fg456;7661b145!-1;78200;-60584;S!0;-200;-1575!1;-4416;"
|
657 |
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"660!2;-2431;651!3;167;0;L!}";
|
658 |
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659 |
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|
660 |
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NET "ram1_ddr2_dq_in_falling<2>"
|
661 |
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ROUTE="{3;1;3s1000fg456;c6f6b973!-1;78200;-57528;S!0;-208;-1247!1;-4376;"
|
662 |
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"-2748!2;-3921;4059!3;1458;-352!4;167;0;L!}";
|
663 |
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|
664 |
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|
665 |
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NET "ram1_ddr2_dq_in_falling<3>"
|
666 |
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ROUTE="{3;1;3s1000fg456;c9079a8c!-1;78200;-57208;S!0;-200;-1575!1;-4416;"
|
667 |
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"660!2;-2431;651!3;167;0;L!}";
|
668 |
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|
669 |
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670 |
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NET "ram1_ddr2_dq_in_falling<4>"
|
671 |
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ROUTE="{3;1;3s1000fg456;ea4a07da!-1;78200;-53904;S!0;-200;-1379!1;-4416;"
|
672 |
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"784!2;-2431;307!3;167;0;L!}";
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673 |
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674 |
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675 |
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NET "ram1_ddr2_dq_in_falling<5>"
|
676 |
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ROUTE="{3;1;3s1000fg456;38a2ee33!-1;78200;-53584;S!0;-208;-1691!1;-4376;"
|
677 |
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"-2872!2;-3921;4307!3;1458;-8!4;167;0;L!}";
|
678 |
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679 |
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|
680 |
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NET "ram1_ddr2_dq_in_falling<6>"
|
681 |
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ROUTE="{3;1;3s1000fg456;5453682b!-1;78200;-50528;S!0;-2043;-592!1;-6173;"
|
682 |
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"-65!2;1169;369!3;167;0;L!}";
|
683 |
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684 |
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685 |
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NET "ram1_ddr2_dq_in_falling<7>"
|
686 |
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ROUTE="{3;1;3s1000fg456;e227436c!-1;78200;-50208;S!0;-200;-1575!1;-4416;"
|
687 |
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"660!2;-2431;651!3;167;0;L!}";
|
688 |
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689 |
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|
690 |
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NET "ram1_ddr2_dq_in_falling<8>"
|
691 |
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ROUTE="{3;1;3s1000fg456;449aea95!-1;78200;-37024;S!0;-200;-1255!1;-4416;"
|
692 |
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"660!2;-2431;307!3;167;0;L!}";
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693 |
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694 |
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695 |
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NET "ram1_ddr2_dq_in_falling<9>"
|
696 |
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ROUTE="{3;1;3s1000fg456;51241ec9!-1;78200;-36704;S!0;-208;-1567!1;-4376;"
|
697 |
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"-2748!2;-3921;4059!3;1458;-8!4;167;0;L!}";
|
698 |
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699 |
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|
700 |
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NET "ram1_ddr2_dq_in_falling<10>"
|
701 |
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ROUTE="{3;1;3s1000fg456;57f25b81!-1;78200;-13144;S!0;-2043;-592!1;-6173;"
|
702 |
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"-65!2;1169;369!3;167;0;L!}";
|
703 |
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704 |
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705 |
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NET "ram1_ddr2_dq_in_falling<11>"
|
706 |
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ROUTE="{3;1;3s1000fg456;20aea785!-1;78200;-12824;S!0;-200;-1575!1;-4416;"
|
707 |
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"660!2;-2431;651!3;167;0;L!}";
|
708 |
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|
709 |
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710 |
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NET "ram1_ddr2_dq_in_falling<12>"
|
711 |
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ROUTE="{3;1;3s1000fg456;edddf5a8!-1;78200;-9768;S!0;-200;-1255!1;-4416;"
|
712 |
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"660!2;-2431;307!3;167;0;L!}";
|
713 |
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714 |
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715 |
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#NET "ram1_ddr2_dq_in_falling<13>"
|
716 |
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#ROUTE="{3;1;3s1000fg456;c0afe05e!-1;78200;-9448;S!0;-192;1793!1;-4408;"
|
717 |
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#"-712!2;-2447;-665!3;0;-680!4;167;0;L!}";
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718 |
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719 |
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720 |
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NET "ram1_ddr2_dq_in_falling<14>"
|
721 |
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ROUTE="{3;1;3s1000fg456;fcfec485!-1;78200;928;S!0;-200;-1699!1;-4416;784!"
|
722 |
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"2;-2431;307!3;167;0;L!}";
|
723 |
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724 |
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725 |
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NET "ram1_ddr2_dq_in_falling<15>"
|
726 |
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ROUTE="{3;1;3s1000fg456;fa72f8a1!-1;78200;-3016;S!0;-1851;2320!1;-6365;"
|
727 |
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"647!2;1169;713!3;167;0;L!}";
|
728 |
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729 |
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730 |
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NET "ram1_ddr2_dq_in_rising<0>"
|
731 |
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ROUTE="{3;1;3s1000fg456;bbef0d49!-1;78200;-60896;S!0;-2067;-608!1;-1524;"
|
732 |
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"648!2;0;-336!3;167;0;L!}";
|
733 |
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|
734 |
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735 |
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NET "ram1_ddr2_dq_in_rising<1>"
|
736 |
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ROUTE="{3;1;3s1000fg456;c756ef03!-1;78200;-60576;S!0;-2043;-920!1;-1548;"
|
737 |
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"648!2;167;0;L!}";
|
738 |
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|
739 |
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|
740 |
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NET "ram1_ddr2_dq_in_rising<2>"
|
741 |
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ROUTE="{3;1;3s1000fg456;f6516412!-1;78200;-57520;S!0;-2043;-600!1;-1548;"
|
742 |
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"304!2;167;0;L!}";
|
743 |
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744 |
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745 |
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NET "ram1_ddr2_dq_in_rising<3>"
|
746 |
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ROUTE="{3;1;3s1000fg456;294eb63a!-1;78200;-57200;S!0;-2067;-928!1;-1524;"
|
747 |
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"648!2;0;8!3;167;0;L!}";
|
748 |
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|
749 |
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|
750 |
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NET "ram1_ddr2_dq_in_rising<4>"
|
751 |
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ROUTE="{3;1;3s1000fg456;ec1b6420!-1;78200;-53896;S!0;-2043;-600!1;-1548;"
|
752 |
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"304!2;167;0;L!}";
|
753 |
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|
754 |
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|
755 |
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NET "ram1_ddr2_dq_in_rising<5>"
|
756 |
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|
ROUTE="{3;1;3s1000fg456;70685ea7!-1;78200;-53576;S!0;-2067;-928!1;-1524;"
|
757 |
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|
"648!2;0;8!3;167;0;L!}";
|
758 |
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|
759 |
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|
760 |
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NET "ram1_ddr2_dq_in_rising<6>"
|
761 |
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ROUTE="{3;1;3s1000fg456;545d66cf!-1;78200;-50520;S!0;-2067;-608!1;-1524;"
|
762 |
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"648!2;0;-336!3;167;0;L!}";
|
763 |
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|
764 |
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|
765 |
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NET "ram1_ddr2_dq_in_rising<7>"
|
766 |
|
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ROUTE="{3;1;3s1000fg456;19b5df66!-1;78200;-50200;S!0;-2059;1080!1;-1532;"
|
767 |
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"-672!2;0;-680!3;167;0;L!}";
|
768 |
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|
769 |
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|
770 |
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NET "ram1_ddr2_dq_in_rising<8>"
|
771 |
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|
ROUTE="{3;1;3s1000fg456;74da3fd2!-1;78200;-37016;S!0;-2067;-608!1;-1524;"
|
772 |
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|
"648!2;0;-336!3;167;0;L!}";
|
773 |
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774 |
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|
775 |
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NET "ram1_ddr2_dq_in_rising<9>"
|
776 |
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ROUTE="{3;1;3s1000fg456;1d6ea017!-1;78200;-36696;S!0;-2043;-920!1;-1548;"
|
777 |
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|
"648!2;167;0;L!}";
|
778 |
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779 |
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780 |
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NET "ram1_ddr2_dq_in_rising<10>"
|
781 |
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ROUTE="{3;1;3s1000fg456;15b0e694!-1;78200;-13136;S!0;-2067;-608!1;-1524;"
|
782 |
|
|
"648!2;0;-336!3;167;0;L!}";
|
783 |
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|
784 |
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|
785 |
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#NET "ram1_ddr2_dq_in_rising<11>"
|
786 |
|
|
#ROUTE="{3;1;3s1000fg456;6c91ddfb!-1;78200;-12816;S!0;-2059;1080!1;-1532;"
|
787 |
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#"-672!2;0;-680!3;167;0;L!}";
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788 |
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789 |
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790 |
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NET "ram1_ddr2_dq_in_rising<12>"
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791 |
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ROUTE="{3;1;3s1000fg456;8122bee4!-1;78200;-9760;S!0;-2067;-608!1;-1524;"
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792 |
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"648!2;0;-336!3;167;0;L!}";
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793 |
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794 |
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795 |
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NET "ram1_ddr2_dq_in_rising<13>"
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796 |
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ROUTE="{3;1;3s1000fg456;82dd67b9!-1;78200;-9440;S!0;-2043;-920!1;-1548;"
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797 |
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"648!2;167;0;L!}";
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798 |
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799 |
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800 |
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NET "ram1_ddr2_dq_in_rising<14>"
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801 |
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ROUTE="{3;1;3s1000fg456;1af6bfb9!-1;78200;936;S!0;-2043;-920!1;-1548;304!"
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802 |
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"2;167;0;L!}";
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803 |
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804 |
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805 |
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NET "ram1_ddr2_dq_in_rising<15>"
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806 |
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ROUTE="{3;1;3s1000fg456;77ad7fbf!-1;78200;-3008;S!0;-2059;1400!1;-1532;"
|
807 |
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"2272!2;167;0;L!}";
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808 |
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809 |
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810 |
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811 |
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812 |
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// 06/06 @ 11:05:52
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813 |
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NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in0"
|
814 |
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ROUTE="{3;1;3s1000fg456;f7a7e793!-1;74936;-63664;S!0;-384;1497!1;-12136;"
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815 |
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"-612!2;6825;59387!2;10281;59387!3;200;-50224!4;200;-50224!5;2039;-6928;L!"
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816 |
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"5;2039;3448;L!5;2039;3792;L!5;1879;-7616;L!5;1879;-7272;L!5;1879;-4240;L!"
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817 |
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"5;1879;-3896;L!5;1879;-616;L!5;1879;-272;L!5;1879;2760;L!5;1879;3104;L!6;"
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818 |
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"2039;3448;L!6;2039;3792;L!6;1879;-7616;L!6;1879;-7272;L!6;1879;-4240;L!6;"
|
819 |
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"1879;-3896;L!6;1879;-616;L!6;1879;-272;L!6;1879;2760;L!6;1879;3104;L!6;"
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820 |
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"2039;-6928;L!}";
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821 |
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822 |
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823 |
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NET "ram1_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in1"
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824 |
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ROUTE="{3;1;3s1000fg456;839ff060!-1;74936;-36408;S!0;-384;1497!1;-12136;"
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825 |
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"-612!2;6276;28368!2;9732;28368!3;763;1043!3;749;-19205!4;763;1043!4;749;"
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826 |
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"-19205!5;2025;7080;L!5;2025;7424;L!5;1865;-7360;L!5;1865;-7016;L!5;1865;"
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827 |
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"-3984;L!5;1865;-3640;L!5;1865;6392;L!5;1865;6736;L!6;1879;-10992;L!6;"
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828 |
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"1879;-10648;L!6;2039;-10304;L!7;2025;7080;L!7;2025;7424;L!7;1865;-7360;L!"
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829 |
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"7;1865;-7016;L!7;1865;-3984;L!7;1865;-3640;L!7;1865;6392;L!7;1865;6736;L!"
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830 |
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"8;2039;-10304;L!8;1879;-10992;L!8;1879;-10648;L!}";
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831 |
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832 |
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833 |
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NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in0"
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834 |
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ROUTE="{3;1;3s1000fg456;43f880d9!-1;74936;62488;S!0;-384;1497!1;-12136;"
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835 |
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"-612!2;6849;-63157!2;10305;-63157!3;190;51560!3;176;72320!4;190;51560!4;"
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836 |
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"176;72320!5;2025;80;L!5;1865;-608;L!5;1865;-264;L!5;1865;3016;L!5;1865;"
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837 |
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"3360;L!5;1865;6392;L!5;1865;6736;L!6;2039;-6928;L!6;2039;-6584;L!6;1879;"
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838 |
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"-7616;L!6;1879;-7272;L!7;1865;-608;L!7;1865;-264;L!7;1865;3016;L!7;1865;"
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839 |
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"3360;L!7;1865;6392;L!7;1865;6736;L!7;2025;80;L!8;2039;-6928;L!8;2039;"
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840 |
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"-6584;L!8;1879;-7616;L!8;1879;-7272;L!}";
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841 |
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842 |
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843 |
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NET "ram2_ddr2_iobs/datapath_ddr2_iobs0/dqs_int_delay_in1"
|
844 |
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ROUTE="{3;1;3s1000fg456;ee14069!-1;74936;35232;S!0;-384;1497!1;-12136;"
|
845 |
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"-612!2;6300;-32944!2;9756;-32944!3;725;41859!3;725;1099!3;739;21347!4;"
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846 |
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"725;41859!4;725;1099!4;739;21347!5;2039;-3304;L!5;2039;-2960;L!5;1879;"
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847 |
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"-10744;L!5;1879;-10400;L!5;1879;-3992;L!5;1879;-3648;L!6;1879;6480;L!6;"
|
848 |
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"1879;6136;L!6;1879;2760;L!6;2039;3792;L!7;1865;-10736;L!8;2039;-3304;L!8;"
|
849 |
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"2039;-2960;L!8;1879;-10744;L!8;1879;-10400;L!8;1879;-3992;L!8;1879;-3648;"
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850 |
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"L!9;1879;6480;L!9;1879;6136;L!9;1879;2760;L!9;2039;3792;L!10;1865;-10736;"
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851 |
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"L!}";
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852 |
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853 |
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854 |
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