Subversion Repositories pulse_processing_algorithm

-- fifo_wr_addr gray counter with synchronous reset

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

ENTITY wr_gray_cntr IS

        port (

                        clk                             :       in std_logic;

                        reset                           :       in std_logic;

                        cnt_en                          :       in std_logic;

                        wgc_gcnt                        :       out     std_logic_vector(3 downto 0)

                  );

END wr_gray_cntr ;

ARCHITECTURE wr_gray_cntr OF wr_gray_cntr IS

component FDCE

    port(

      Q                              :  out   STD_ULOGIC;

      C                              :  in    STD_ULOGIC;

      CE                             :  in    STD_ULOGIC;

      CLR                            :  in    STD_ULOGIC;

      D                              :  in    STD_ULOGIC

      );

end component;

-- gray encoded signals

signal  d0      :       STD_ULOGIC;

signal  d1      :       STD_ULOGIC;

signal  d2      :       STD_ULOGIC;

signal  d3      :       STD_ULOGIC;

signal  gc_int :  std_logic_vector(3 downto 0);

BEGIN

    wgc_gcnt <= gc_int(3 downto 0);

    d0 <=  ( (not gc_int(3)) and (not gc_int(2)) and (not gc_int(1)) ) or ( gc_int(3) and gc_int(2) and (not gc_int(1)) ) or ( gc_int(3) and (not gc_int(2)) and gc_int(1) ) or ( (not gc_int(3)) and gc_int(2) and gc_int(1) );

---    d0 <= ( not gc_int(1) and ( gc_int(3) xnor gc_int(2))) or (gc_int(1) and ( gc_int(3) xor gc_int(2)));

    d1 <= ( gc_int(1) and (not gc_int(0)) ) or ( (not gc_int(3)) and (not gc_int(2)) and gc_int(0) ) or ( gc_int(3) and gc_int(2) and gc_int(0) );

    d2 <= ( (not gc_int(3)) and gc_int(1) and (not gc_int(0)) ) or ( gc_int(2) and (not gc_int(1)) ) or ( gc_int(2) and gc_int(0) );

    d3 <= ( gc_int(2) and (not gc_int(1)) and (not gc_int(0)) ) or ( gc_int(3) and gc_int(0) ) or ( gc_int(3) and gc_int(1) );

bit0 : FDCE port map (

                      Q   => gc_int(0),

                      C   => clk,

                      CE  => cnt_en,

                      CLR => reset,

                      D   => d0

                     );

bit1 : FDCE port map (

                      Q   => gc_int(1),

                      C   => clk,

                      CE  => cnt_en,

                      CLR => reset,

                      D   => d1

                     );

bit2 : FDCE port map (

                      Q   => gc_int(2),

                      C   => clk,

                      CE  => cnt_en,

                      CLR => reset,

                      D   => d2

                     );

bit3 : FDCE port map (

                      Q   => gc_int(3),

                      C   => clk,

                      CE  => cnt_en,

                      CLR => reset,

                      D   => d3

                     );

END wr_gray_cntr;