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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetOperandRegs.v] - Blame information for rev 44

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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2011,2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_SetOperandRegs.v
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// If a register field is not used by an instruction, then the register
// selected is forced to r0 for that field. This causes load stalls to be
// avoided, which would otherwise occur.
//=============================================================================
 
module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);
input rst;
input clk;
input advanceI;
input advanceR;
input advanceX;
input [63:0] b;
input [3:0] AXC;
input [31:0] insn;
input [31:0] xIR;
output [8:0] dRa;
reg [8:0] dRa;
output [8:0] dRb;
reg [8:0] dRb;
output [8:0] dRc;
reg [8:0] dRc;
 
wire [6:0] iOpcode = insn[31:25];
wire [6:0] xOpcode = xIR[31:25];
wire [5:0] xFunc = xIR[5:0];
wire [6:0] iFunc7 = insn[6:0];
 
always @(posedge clk)
if (rst) begin
        dRa <= 9'd0;
        dRb <= 9'd0;
        dRc <= 9'd0;
end
else begin
        if (advanceI) begin
                // Default settings, to be overridden
                dRa <= {AXC,insn[24:20]};
                dRb <= {AXC,insn[19:15]};
                dRc <= {AXC,insn[14:10]};
                casex(iOpcode)
                `MISC:
                        case(iFunc7)
                        `IRET:  begin
                                        dRa <= {AXC,5'd25};
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                        `ERET:  begin
                                        dRa <= {AXC,5'd24};
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                        default:
                                        begin
                                        dRa <= 9'd0;
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                        endcase
                `R:     begin dRb <= 9'd0; dRc <= 9'd0; end
                `RR: dRc <= 9'd0;
                `TRAPcc:        dRc <= 9'd0;
                `TRAPcci:       begin dRb <= 9'd0; dRc <= 9'd0; end
                `CALL,`JMP,`NOPI:
                                        begin
                                        dRa <= 9'd0;
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `RET:           begin
                                        dRa <= {AXC,5'd30};
                                        dRb <= {AXC,5'd31};
                                        dRc <= 9'd0;
                                        end
                `LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
                                        dRc <= 9'd0;
                `INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `OUTB,`OUTC,`OUTH,`OUTW:
                                        dRc <= 9'd0;
                `BLTI,`BLEI,`BGTI,`BGEI,
                `BLTUI,`BLEUI,`BGTUI,`BGEUI,
                `BEQI,`BNEI:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `BTRI:          dRc <= 9'd0;
                `SLTI,`SLEI,`SGTI,`SGEI,
                `SLTUI,`SLEUI,`SGTUI,`SGEUI,
                `SEQI,`SNEI:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
                `ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `JAL:
                                        begin
                                        dRb <= 9'd0;
                                        dRc <= 9'd0;
                                        end
                `SETLO:         begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
                `SETMID:        begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
                `SETHI:         begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
                default:        dRa <= {AXC,insn[24:20]};
                endcase
        end
        else if (advanceR) begin
                dRa <= 9'd0;
                dRb <= 9'd0;
                dRc <= 9'd0;
        end
        // no else here
        if (advanceX) begin
                if (xOpcode==`R) begin
                        if (xFunc==`EXEC) begin
                                dRa <= b[24:20];
                                dRb <= b[19:15];
                                dRc <= b[14:10];
                        end
                end
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	33	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2011,2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_SetOperandRegs.v`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26	41	robfinch	`// If a register field is not used by an instruction, then the register`
27			`// selected is forced to r0 for that field. This causes load stalls to be`
28			`// avoided, which would otherwise occur.`
29	33	robfinch	`//=============================================================================`
30
31			`module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, insn, xIR, dRa, dRb, dRc);`
32			`input rst;`
33			`input clk;`
34			`input advanceI;`
35			`input advanceR;`
36			`input advanceX;`
37			`input [63:0] b;`
38			`input [3:0] AXC;`
39	41	robfinch	`input [31:0] insn;`
40			`input [31:0] xIR;`
41	33	robfinch	`output [8:0] dRa;`
42			`reg [8:0] dRa;`
43			`output [8:0] dRb;`
44			`reg [8:0] dRb;`
45			`output [8:0] dRc;`
46			`reg [8:0] dRc;`
47
48	41	robfinch	`wire [6:0] iOpcode = insn[31:25];`
49			`wire [6:0] xOpcode = xIR[31:25];`
50			`wire [5:0] xFunc = xIR[5:0];`
51			`wire [6:0] iFunc7 = insn[6:0];`
52	33	robfinch
53			`always @(posedge clk)`
54			`if (rst) begin`
55			`dRa <= 9'd0;`
56			`dRb <= 9'd0;`
57			`dRc <= 9'd0;`
58			`end`
59			`else begin`
60			`if (advanceI) begin`
61			`// Default settings, to be overridden`
62	41	robfinch	`dRa <= {AXC,insn[24:20]};`
63			`dRb <= {AXC,insn[19:15]};`
64			`dRc <= {AXC,insn[14:10]};`
65	33	robfinch	`casex(iOpcode)`
66	41	robfinch	`MISC:
67			`case(iFunc7)`
68			`IRET: begin
69			`dRa <= {AXC,5'd25};`
70			`dRb <= 9'd0;`
71			`dRc <= 9'd0;`
72			`end`
73			`ERET: begin
74			`dRa <= {AXC,5'd24};`
75			`dRb <= 9'd0;`
76			`dRc <= 9'd0;`
77			`end`
78			`default:`
79			`begin`
80			`dRa <= 9'd0;`
81			`dRb <= 9'd0;`
82			`dRc <= 9'd0;`
83			`end`
84			`endcase`
85	44	robfinch	`R: begin dRb <= 9'd0; dRc <= 9'd0; end
86			`RR: dRc <= 9'd0;
87			`TRAPcc: dRc <= 9'd0;
88			`TRAPcci: begin dRb <= 9'd0; dRc <= 9'd0; end
89	41	robfinch	`CALL,`JMP,`NOPI:
90			`begin`
91			`dRa <= 9'd0;`
92			`dRb <= 9'd0;`
93			`dRc <= 9'd0;`
94			`end`
95	33	robfinch	`RET: begin
96			`dRa <= {AXC,5'd30};`
97			`dRb <= {AXC,5'd31};`
98	41	robfinch	`dRc <= 9'd0;`
99	33	robfinch	`end`
100	44	robfinch	`LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
101			`begin`
102			`dRb <= 9'd0;`
103			`dRc <= 9'd0;`
104			`end`
105			`SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
106			`dRc <= 9'd0;`
107			`INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
108			`begin`
109			`dRb <= 9'd0;`
110			`dRc <= 9'd0;`
111			`end`
112			`OUTB,`OUTC,`OUTH,`OUTW:
113			`dRc <= 9'd0;`
114	41	robfinch	`BLTI,`BLEI,`BGTI,`BGEI,
115			`BLTUI,`BLEUI,`BGTUI,`BGEUI,
116			`BEQI,`BNEI:
117			`begin`
118			`dRb <= 9'd0;`
119			`dRc <= 9'd0;`
120			`end`
121	44	robfinch	`BTRI: dRc <= 9'd0;
122	41	robfinch	`SLTI,`SLEI,`SGTI,`SGEI,
123			`SLTUI,`SLEUI,`SGTUI,`SGEUI,
124			`SEQI,`SNEI:
125			`begin`
126			`dRb <= 9'd0;`
127			`dRc <= 9'd0;`
128			`end`
129	44	robfinch	`ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
130			`ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
131			`begin`
132			`dRb <= 9'd0;`
133			`dRc <= 9'd0;`
134			`end`
135			`JAL:
136			`begin`
137			`dRb <= 9'd0;`
138			`dRc <= 9'd0;`
139			`end`
140			`SETLO: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
141			`SETMID: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
142			`SETHI: begin dRa <= {AXC,insn[26:22]}; dRb <= 9'd0; dRc <= 9'd0; end
143	41	robfinch	`default: dRa <= {AXC,insn[24:20]};`
144	33	robfinch	`endcase`
145			`end`
146			`else if (advanceR) begin`
147			`dRa <= 9'd0;`
148			`dRb <= 9'd0;`
149			`dRc <= 9'd0;`
150			`end`
151			`// no else here`
152			`if (advanceX) begin`
153			if (xOpcode==`R) begin
154			if (xFunc==`EXEC) begin
155	41	robfinch	`dRa <= b[24:20];`
156			`dRb <= b[19:15];`
157			`dRc <= b[14:10];`
158	33	robfinch	`end`
159			`end`
160			`end`
161			`end`
162
163			`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetOperandRegs.v] - Blame information for rev 44