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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetOperandRegs.v] - Blame information for rev 48

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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2011,2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_SetOperandRegs.v
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// If a register field is not used by an instruction, then the register
// selected is forced to r0 for that field. This causes load stalls to be
// avoided, which would otherwise occur.
//=============================================================================
 
module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, xAXC, insn, xIR, dRa, dRb, dRc, nxt_Ra, nxt_Rb, nxt_Rc);
input rst;
input clk;
input advanceI;
input advanceR;
input advanceX;
input [63:0] b;
input [3:0] AXC;
input [3:0] xAXC;
input [31:0] insn;
input [31:0] xIR;
output [8:0] dRa;
reg [8:0] dRa;
output [8:0] dRb;
reg [8:0] dRb;
output [8:0] dRc;
reg [8:0] dRc;
output [8:0] nxt_Ra;
reg [8:0] nxt_Ra;
output [8:0] nxt_Rb;
reg [8:0] nxt_Rb;
output [8:0] nxt_Rc;
reg [8:0] nxt_Rc;
 
wire [6:0] iOpcode = insn[31:25];
wire [6:0] xOpcode = xIR[31:25];
wire [5:0] xFunc = xIR[5:0];
wire [6:0] iFunc7 = insn[6:0];
 
 
always @*
begin
        nxt_Ra <= dRa;
        nxt_Rb <= dRb;
        nxt_Rc <= dRc;
        if (advanceI) begin
                // Default settings, to be overridden
                nxt_Ra <= {AXC,insn[24:20]};
                nxt_Rb <= {AXC,insn[19:15]};
                nxt_Rc <= {AXC,insn[14:10]};
                casex(iOpcode)
                `MISC:
                        case(iFunc7)
                        `IRET:  begin
                                        nxt_Ra <= {AXC,5'd25};
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                        `ERET:  begin
                                        nxt_Ra <= {AXC,5'd24};
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                        default:
                                        begin
                                        nxt_Ra <= 9'd0;
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                        endcase
                `R:     begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
                `RR: nxt_Rc <= 9'd0;
                `TRAPcc:        nxt_Rc <= 9'd0;
                `TRAPcci:       begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
                `CALL,`JMP,`NOPI:
                                        begin
                                        nxt_Ra <= 9'd0;
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `RET:           begin
                                        nxt_Ra <= {AXC,5'd30};
                                        nxt_Rb <= {AXC,5'd31};
                                        nxt_Rc <= 9'd0;
                                        end
                `LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
                                        nxt_Rc <= 9'd0;
                `INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `OUTB,`OUTC,`OUTH,`OUTW:
                                        nxt_Rc <= 9'd0;
                `BLTI,`BLEI,`BGTI,`BGEI,
                `BLTUI,`BLEUI,`BGTUI,`BGEUI,
                `BEQI,`BNEI:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `BTRI:          nxt_Rc <= 9'd0;
                `SLTI,`SLEI,`SGTI,`SGEI,
                `SLTUI,`SLEUI,`SGTUI,`SGEUI,
                `SEQI,`SNEI:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
                `ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `JAL:
                                        begin
                                        nxt_Rb <= 9'd0;
                                        nxt_Rc <= 9'd0;
                                        end
                `SETLO:         begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
                `SETMID:        begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
                `SETHI:         begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
                default:        nxt_Ra <= {AXC,insn[24:20]};
                endcase
        end
        else if (advanceR) begin
                nxt_Ra <= 9'd0;
                nxt_Rb <= 9'd0;
                nxt_Rc <= 9'd0;
        end
        // no else here
        if (advanceX) begin
                if (xOpcode==`R) begin
                        if (xFunc==`EXEC) begin
                                nxt_Ra <= {xAXC,b[24:20]};
                                nxt_Rb <= {xAXC,b[19:15]};
                                nxt_Rc <= {xAXC,b[14:10]};
                        end
                end
        end
end
 
always @(posedge clk)
if (rst) begin
        dRa <= 9'd0;
        dRb <= 9'd0;
        dRc <= 9'd0;
end
else begin
        dRa <= nxt_Ra;
        dRb <= nxt_Rb;
        dRc <= nxt_Rc;
end
 
endmodule

Line No.	Rev	Author	Line
1	33	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2011,2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_SetOperandRegs.v`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26	41	robfinch	`// If a register field is not used by an instruction, then the register`
27			`// selected is forced to r0 for that field. This causes load stalls to be`
28			`// avoided, which would otherwise occur.`
29	33	robfinch	`//=============================================================================`
30
31	48	robfinch	`module Raptor64_SetOperandRegs(rst, clk, advanceI, advanceR, advanceX, b, AXC, xAXC, insn, xIR, dRa, dRb, dRc, nxt_Ra, nxt_Rb, nxt_Rc);`
32	33	robfinch	`input rst;`
33			`input clk;`
34			`input advanceI;`
35			`input advanceR;`
36			`input advanceX;`
37			`input [63:0] b;`
38			`input [3:0] AXC;`
39	45	robfinch	`input [3:0] xAXC;`
40	41	robfinch	`input [31:0] insn;`
41			`input [31:0] xIR;`
42	33	robfinch	`output [8:0] dRa;`
43			`reg [8:0] dRa;`
44			`output [8:0] dRb;`
45			`reg [8:0] dRb;`
46			`output [8:0] dRc;`
47			`reg [8:0] dRc;`
48	48	robfinch	`output [8:0] nxt_Ra;`
49			`reg [8:0] nxt_Ra;`
50			`output [8:0] nxt_Rb;`
51			`reg [8:0] nxt_Rb;`
52			`output [8:0] nxt_Rc;`
53			`reg [8:0] nxt_Rc;`
54	33	robfinch
55	41	robfinch	`wire [6:0] iOpcode = insn[31:25];`
56			`wire [6:0] xOpcode = xIR[31:25];`
57			`wire [5:0] xFunc = xIR[5:0];`
58			`wire [6:0] iFunc7 = insn[6:0];`
59	33	robfinch
60	48	robfinch
61			`always @*`
62			`begin`
63			`nxt_Ra <= dRa;`
64			`nxt_Rb <= dRb;`
65			`nxt_Rc <= dRc;`
66	33	robfinch	`if (advanceI) begin`
67			`// Default settings, to be overridden`
68	48	robfinch	`nxt_Ra <= {AXC,insn[24:20]};`
69			`nxt_Rb <= {AXC,insn[19:15]};`
70			`nxt_Rc <= {AXC,insn[14:10]};`
71	33	robfinch	`casex(iOpcode)`
72	41	robfinch	`MISC:
73			`case(iFunc7)`
74			`IRET: begin
75	48	robfinch	`nxt_Ra <= {AXC,5'd25};`
76			`nxt_Rb <= 9'd0;`
77			`nxt_Rc <= 9'd0;`
78	41	robfinch	`end`
79			`ERET: begin
80	48	robfinch	`nxt_Ra <= {AXC,5'd24};`
81			`nxt_Rb <= 9'd0;`
82			`nxt_Rc <= 9'd0;`
83	41	robfinch	`end`
84			`default:`
85			`begin`
86	48	robfinch	`nxt_Ra <= 9'd0;`
87			`nxt_Rb <= 9'd0;`
88			`nxt_Rc <= 9'd0;`
89	41	robfinch	`end`
90			`endcase`
91	48	robfinch	`R: begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
92			`RR: nxt_Rc <= 9'd0;
93			`TRAPcc: nxt_Rc <= 9'd0;
94			`TRAPcci: begin nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
95	41	robfinch	`CALL,`JMP,`NOPI:
96			`begin`
97	48	robfinch	`nxt_Ra <= 9'd0;`
98			`nxt_Rb <= 9'd0;`
99			`nxt_Rc <= 9'd0;`
100	41	robfinch	`end`
101	33	robfinch	`RET: begin
102	48	robfinch	`nxt_Ra <= {AXC,5'd30};`
103			`nxt_Rb <= {AXC,5'd31};`
104			`nxt_Rc <= 9'd0;`
105	33	robfinch	`end`
106	44	robfinch	`LB,`LBU,`LH,`LHU,`LC,`LCU,`LW,`LP,`LSH,`LSW,`LF,`LFD,`LFP,`LFDP,`LWR:
107			`begin`
108	48	robfinch	`nxt_Rb <= 9'd0;`
109			`nxt_Rc <= 9'd0;`
110	44	robfinch	`end`
111			`SB,`SC,`SH,`SW,`SP,`SSH,`SSW,`SF,`SFD,`SFP,`SFDP,`SWC:
112	48	robfinch	`nxt_Rc <= 9'd0;`
113	44	robfinch	`INB,`INBU,`INCH,`INCU,`INH,`INHU,`INW:
114			`begin`
115	48	robfinch	`nxt_Rb <= 9'd0;`
116			`nxt_Rc <= 9'd0;`
117	44	robfinch	`end`
118			`OUTB,`OUTC,`OUTH,`OUTW:
119	48	robfinch	`nxt_Rc <= 9'd0;`
120	41	robfinch	`BLTI,`BLEI,`BGTI,`BGEI,
121			`BLTUI,`BLEUI,`BGTUI,`BGEUI,
122			`BEQI,`BNEI:
123			`begin`
124	48	robfinch	`nxt_Rb <= 9'd0;`
125			`nxt_Rc <= 9'd0;`
126	41	robfinch	`end`
127	48	robfinch	`BTRI: nxt_Rc <= 9'd0;
128	41	robfinch	`SLTI,`SLEI,`SGTI,`SGEI,
129			`SLTUI,`SLEUI,`SGTUI,`SGEUI,
130			`SEQI,`SNEI:
131			`begin`
132	48	robfinch	`nxt_Rb <= 9'd0;`
133			`nxt_Rc <= 9'd0;`
134	41	robfinch	`end`
135	44	robfinch	`ADDI,`ADDUI,`SUBI,`SUBUI,`CMPI,`CMPUI,
136			`ANDI,`XORI,`ORI,`MULUI,`MULSI,`DIVUI,`DIVSI:
137			`begin`
138	48	robfinch	`nxt_Rb <= 9'd0;`
139			`nxt_Rc <= 9'd0;`
140	44	robfinch	`end`
141			`JAL:
142			`begin`
143	48	robfinch	`nxt_Rb <= 9'd0;`
144			`nxt_Rc <= 9'd0;`
145	44	robfinch	`end`
146	48	robfinch	`SETLO: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
147			`SETMID: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
148			`SETHI: begin nxt_Ra <= {AXC,insn[26:22]}; nxt_Rb <= 9'd0; nxt_Rc <= 9'd0; end
149			`default: nxt_Ra <= {AXC,insn[24:20]};`
150	33	robfinch	`endcase`
151			`end`
152			`else if (advanceR) begin`
153	48	robfinch	`nxt_Ra <= 9'd0;`
154			`nxt_Rb <= 9'd0;`
155			`nxt_Rc <= 9'd0;`
156	33	robfinch	`end`
157			`// no else here`
158			`if (advanceX) begin`
159			if (xOpcode==`R) begin
160			if (xFunc==`EXEC) begin
161	48	robfinch	`nxt_Ra <= {xAXC,b[24:20]};`
162			`nxt_Rb <= {xAXC,b[19:15]};`
163			`nxt_Rc <= {xAXC,b[14:10]};`
164	33	robfinch	`end`
165			`end`
166			`end`
167			`end`
168
169	48	robfinch	`always @(posedge clk)`
170			`if (rst) begin`
171			`dRa <= 9'd0;`
172			`dRb <= 9'd0;`
173			`dRc <= 9'd0;`
174			`end`
175			`else begin`
176			`dRa <= nxt_Ra;`
177			`dRb <= nxt_Rb;`
178			`dRc <= nxt_Rc;`
179			`end`
180
181	33	robfinch	`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetOperandRegs.v] - Blame information for rev 48