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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2011,2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_TLB.v
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// TLB
// The TLB contains 64 entries, that are 8 way set associative.
// The TLB is dual ported and shared between the instruction and data streams.
//
//=============================================================================
//
`define TLBMissPage             52'hFFFF_FFFF_FFFF_F
 
module Raptor64_TLB(rst, clk, pc, ea, ppc, pea,
        m1IsStore, ASID,
        wTlbp, wTlbrd, wTlbwr, wTlbwi,
        xTlbrd, xTlbwr, xTlbwi,
        wr, wregno, dati, xregno, dato, ITLBMiss, DTLBMiss, HTLBVirtPage);
input rst;
input clk;
input [63:0] pc;
input [63:0] ea;
output [63:0] ppc;
output [63:0] pea;
input m1IsStore;
input [7:0] ASID;
input wTlbp;
input wTlbrd;
input wTlbwr;
input wTlbwi;
input xTlbrd;
input xTlbwr;
input xTlbwi;
input wr;
input [5:0] wregno;
input [63:0] dati;
input [5:0] xregno;
output [63:0] dato;
reg [63:0] dato;
output ITLBMiss;
output DTLBMiss;
output [63:0] HTLBVirtPage;
 
integer n;
 
// Holding registers
// These allow the TLB to updated in a single cycle
reg [24:13] HTLBPageMask;
reg [63:13] HTLBVirtPage;
reg [63:13] HTLBPhysPage0;
reg [63:13] HTLBPhysPage1;
reg [7:0] HTLBASID;
reg HTLBG;
reg HTLBD;
reg HTLBValid;
 
reg [5:0] i;
reg [63:0] Index;
reg [2:0] Random;
reg [2:0] Wired;
reg [15:0] IMatch,DMatch;
 
reg [3:0] m;
reg [3:0] q;
reg [24:13] TLBPageMask [63:0];
reg [63:13] TLBVirtPage [63:0];
reg [63:13] TLBPhysPage0 [63:0];
reg [63:13] TLBPhysPage1 [63:0];
reg [63:0] TLBG;
reg [63:0] TLBD;
reg [7:0] TLBASID [63:0];
reg [63:0] TLBValid;
initial begin
        for (n = 0; n < 64; n = n + 1)
        begin
                TLBPageMask[n] = 0;
                TLBVirtPage[n] = 0;
                TLBPhysPage0[n] = 0;
                TLBPhysPage1[n] = 0;
                TLBG[n] = 0;
                TLBASID[n] = 0;
                TLBValid[n] = 0;
        end
end
 
wire unmappedArea = pc[63:52]==12'hFFD || pc[63:52]==12'hFFE || pc[63:52]==12'hFFF;
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF || ea[63:52]==12'h000;
wire m1UnmappedDataArea = pea[63:52]==12'hFFD || pea[63:52]==12'hFFE || pea[63:52]==12'hFFF || pea[63:52]==12'h000;
 
always @(posedge clk)
if (rst) begin
        Random <= 3'h7;
        Wired <= 3'd0;
end
else begin
        if (Random==Wired)
                Random <= 3'd7;
        else
                Random <= Random - 3'd1;
 
        if (xTlbrd|xTlbwi)
                i <= {Index[5:3],HTLBVirtPage[15:13]};
        if (xTlbwr)
                i <= {Random,HTLBVirtPage[15:13]};
        if (wr) begin
                case(wregno)
                `TLBWired:              Wired <= dati[2:0];
                `TLBIndex:              Index <= dati[5:0];
                `TLBRandom:     Random <= dati[2:0];
                `TLBPageMask:   HTLBPageMask <= dati[63:13];
                `TLBVirtPage:   HTLBVirtPage <= dati[63:13];
                `TLBPhysPage0:  HTLBPhysPage0 <= dati[63:13];
                `TLBPhysPage1:  HTLBPhysPage1 <= dati[63:13];
                `TLBASID:       begin
                                        HTLBValid <= dati[0];
                                        HTLBD <= dati[1];
                                        HTLBG <= dati[2];
                                        HTLBASID <= dati[15:8];
                                        end
                endcase
        end
        if (wTlbp)
                begin
                        Index[63] <= ~|DMatch;
                end
        if (wTlbrd) begin
                HTLBPageMask <= TLBPageMask[i];
                HTLBVirtPage <= TLBVirtPage[i];
                HTLBPhysPage0 <= TLBPhysPage0[i];
                HTLBPhysPage1 <= TLBPhysPage1[i];
                HTLBASID <= TLBASID[i];
                HTLBG <= TLBG[i];
                HTLBD <= TLBD[i];
                HTLBValid <= TLBValid[i];
        end
        else if (wTlbwi) begin
                TLBVirtPage[i] <= HTLBVirtPage;
                TLBPhysPage0[i] <= HTLBPhysPage0;
                TLBPhysPage1[i] <= HTLBPhysPage1;
                TLBASID[i] <= HTLBASID;
                TLBG[i] <= HTLBG;
                TLBD[i] <= HTLBD;
                TLBValid[i] <= HTLBValid;
        end
        else if (wTlbwr) begin
                TLBVirtPage[i] <= HTLBVirtPage;
                TLBPhysPage0[i] <= HTLBPhysPage0;
                TLBPhysPage1[i] <= HTLBPhysPage1;
                TLBASID[i] <= HTLBASID;
                TLBG[i] <= HTLBG;
                TLBD[i] <= HTLBD;
                TLBValid[i] <= HTLBValid;
        end
        // Set the dirty bit on a store
        if (m1IsStore)
                if (!m1UnmappedDataArea & !q[3])
                        TLBD[{q[2:0],pea[15:13]}] <= 1'b1;
end
 
always @*
        case(xregno)
        `TLBWired:              dato = Wired;
        `TLBIndex:              dato = Index;
        `TLBRandom:             dato = Random;
        `TLBPhysPage0:  dato = {HTLBPhysPage0,13'd0};
        `TLBPhysPage1:  dato = {HTLBPhysPage1,13'd0};
        `TLBVirtPage:   dato = {HTLBVirtPage,13'd0};
        `TLBPageMask:   dato = {HTLBPageMask,13'd0};
        `TLBASID:       begin
                                dato = 64'd0;
                                dato[0] = HTLBValid;
                                dato[1] = HTLBD;
                                dato[2] = HTLBG;
                                dato[15:8] = HTLBASID;
                                end
        default:        dato = 64'd0;
        endcase
 
always @*
for (n = 0; n < 8; n = n + 1)
        IMatch[n] = ((pc[63:13]|TLBPageMask[{n[2:0],pc[15:13]}])==(TLBVirtPage[{n[2:0],pc[15:13]}]|TLBPageMask[{n[2:0],pc[15:13]}])) &&
                                ((TLBASID[{n,pc[15:13]}]==ASID) || TLBG[{n,pc[15:13]}]) &&
                                TLBValid[{n,pc[15:13]}];
always @(IMatch)
if (IMatch[0]) m <= 4'd0;
else if (IMatch[1]) m <= 4'd1;
else if (IMatch[2]) m <= 4'd2;
else if (IMatch[3]) m <= 4'd3;
else if (IMatch[4]) m <= 4'd4;
else if (IMatch[5]) m <= 4'd5;
else if (IMatch[6]) m <= 4'd6;
else if (IMatch[7]) m <= 4'd7;
else m <= 4'd15;
 
wire ioddpage = |({TLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);
wire [63:13] IPFN = ioddpage ? TLBPhysPage1[{m[2:0],pc[15:13]}] : TLBPhysPage0[{m[2:0],pc[15:13]}];
 
assign ITLBMiss = !unmappedArea & m[3];
 
assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
assign ppc[12:0] = pc[12:0];
 
always @(ea)
for (n = 0; n < 7; n = n + 1)
        DMatch[n] = ((ea[63:13]|TLBPageMask[{n,ea[15:13]}])==(TLBVirtPage[{n,ea[15:13]}]|TLBPageMask[{n,ea[15:13]}])) &&
                                ((TLBASID[{n,ea[15:13]}]==ASID) || TLBG[{n,ea[15:13]}]) &&
                                TLBValid[{n,ea[15:13]}];
always @(DMatch)
if (DMatch[0]) q <= 4'd0;
else if (DMatch[1]) q <= 4'd1;
else if (DMatch[2]) q <= 4'd2;
else if (DMatch[3]) q <= 4'd3;
else if (DMatch[4]) q <= 4'd4;
else if (DMatch[5]) q <= 4'd5;
else if (DMatch[6]) q <= 4'd6;
else if (DMatch[7]) q <= 4'd7;
else q <= 4'd15;
 
wire doddpage = |({TLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);
wire [63:13] DPFN = doddpage ? TLBPhysPage1[{q[2:0],ea[15:13]}] : TLBPhysPage0[{q[2:0],ea[15:13]}];
 
assign DTLBMiss = !unmappedDataArea & q[3];
 
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
assign pea[12:0] = ea[12:0];
 
endmodule
 

Line No.	Rev	Author	Line
1	30	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2011,2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_TLB.v`
11			`//`
12			`//`
13			`// This source file is free software: you can redistribute it and/or modify`
14			`// it under the terms of the GNU Lesser General Public License as published`
15			`// by the Free Software Foundation, either version 3 of the License, or`
16			`// (at your option) any later version.`
17			`//`
18			`// This source file is distributed in the hope that it will be useful,`
19			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
20			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
21			`// GNU General Public License for more details.`
22			`//`
23			`// You should have received a copy of the GNU General Public License`
24			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
25			`//`
26			`//`
27			`// TLB`
28			`// The TLB contains 64 entries, that are 8 way set associative.`
29			`// The TLB is dual ported and shared between the instruction and data streams.`
30			`//`
31			`//=============================================================================`
32			`//`
33			`define TLBMissPage 52'hFFFF_FFFF_FFFF_F
34
35			`module Raptor64_TLB(rst, clk, pc, ea, ppc, pea,`
36			`m1IsStore, ASID,`
37			`wTlbp, wTlbrd, wTlbwr, wTlbwi,`
38			`xTlbrd, xTlbwr, xTlbwi,`
39			`wr, wregno, dati, xregno, dato, ITLBMiss, DTLBMiss, HTLBVirtPage);`
40			`input rst;`
41			`input clk;`
42			`input [63:0] pc;`
43			`input [63:0] ea;`
44			`output [63:0] ppc;`
45			`output [63:0] pea;`
46			`input m1IsStore;`
47			`input [7:0] ASID;`
48			`input wTlbp;`
49			`input wTlbrd;`
50			`input wTlbwr;`
51			`input wTlbwi;`
52			`input xTlbrd;`
53			`input xTlbwr;`
54			`input xTlbwi;`
55			`input wr;`
56			`input [5:0] wregno;`
57			`input [63:0] dati;`
58			`input [5:0] xregno;`
59			`output [63:0] dato;`
60			`reg [63:0] dato;`
61			`output ITLBMiss;`
62			`output DTLBMiss;`
63			`output [63:0] HTLBVirtPage;`
64
65			`integer n;`
66
67			`// Holding registers`
68			`// These allow the TLB to updated in a single cycle`
69			`reg [24:13] HTLBPageMask;`
70			`reg [63:13] HTLBVirtPage;`
71			`reg [63:13] HTLBPhysPage0;`
72			`reg [63:13] HTLBPhysPage1;`
73			`reg [7:0] HTLBASID;`
74			`reg HTLBG;`
75			`reg HTLBD;`
76			`reg HTLBValid;`
77
78			`reg [5:0] i;`
79			`reg [63:0] Index;`
80			`reg [2:0] Random;`
81			`reg [2:0] Wired;`
82			`reg [15:0] IMatch,DMatch;`
83
84			`reg [3:0] m;`
85			`reg [3:0] q;`
86			`reg [24:13] TLBPageMask [63:0];`
87			`reg [63:13] TLBVirtPage [63:0];`
88			`reg [63:13] TLBPhysPage0 [63:0];`
89			`reg [63:13] TLBPhysPage1 [63:0];`
90			`reg [63:0] TLBG;`
91			`reg [63:0] TLBD;`
92			`reg [7:0] TLBASID [63:0];`
93			`reg [63:0] TLBValid;`
94			`initial begin`
95			`for (n = 0; n < 64; n = n + 1)`
96			`begin`
97			`TLBPageMask[n] = 0;`
98			`TLBVirtPage[n] = 0;`
99			`TLBPhysPage0[n] = 0;`
100			`TLBPhysPage1[n] = 0;`
101			`TLBG[n] = 0;`
102			`TLBASID[n] = 0;`
103			`TLBValid[n] = 0;`
104			`end`
105			`end`
106
107			`wire unmappedArea = pc[63:52]==12'hFFD \|\| pc[63:52]==12'hFFE \|\| pc[63:52]==12'hFFF;`
108	48	robfinch	`wire unmappedDataArea = ea[63:52]==12'hFFD \|\| ea[63:52]==12'hFFE \|\| ea[63:52]==12'hFFF \|\| ea[63:52]==12'h000;`
109			`wire m1UnmappedDataArea = pea[63:52]==12'hFFD \|\| pea[63:52]==12'hFFE \|\| pea[63:52]==12'hFFF \|\| pea[63:52]==12'h000;`
110	30	robfinch
111			`always @(posedge clk)`
112			`if (rst) begin`
113	48	robfinch	`Random <= 3'h7;`
114			`Wired <= 3'd0;`
115	30	robfinch	`end`
116			`else begin`
117			`if (Random==Wired)`
118			`Random <= 3'd7;`
119			`else`
120			`Random <= Random - 3'd1;`
121
122			`if (xTlbrd\|xTlbwi)`
123			`i <= {Index[5:3],HTLBVirtPage[15:13]};`
124			`if (xTlbwr)`
125			`i <= {Random,HTLBVirtPage[15:13]};`
126			`if (wr) begin`
127			`case(wregno)`
128			`TLBWired: Wired <= dati[2:0];
129			`TLBIndex: Index <= dati[5:0];
130			`TLBRandom: Random <= dati[2:0];
131	48	robfinch	`TLBPageMask: HTLBPageMask <= dati[63:13];
132			`TLBVirtPage: HTLBVirtPage <= dati[63:13];
133			`TLBPhysPage0: HTLBPhysPage0 <= dati[63:13];
134			`TLBPhysPage1: HTLBPhysPage1 <= dati[63:13];
135	30	robfinch	`TLBASID: begin
136			`HTLBValid <= dati[0];`
137			`HTLBD <= dati[1];`
138			`HTLBG <= dati[2];`
139			`HTLBASID <= dati[15:8];`
140			`end`
141			`endcase`
142			`end`
143			`if (wTlbp)`
144			`begin`
145			`Index[63] <= ~\|DMatch;`
146			`end`
147			`if (wTlbrd) begin`
148			`HTLBPageMask <= TLBPageMask[i];`
149			`HTLBVirtPage <= TLBVirtPage[i];`
150			`HTLBPhysPage0 <= TLBPhysPage0[i];`
151			`HTLBPhysPage1 <= TLBPhysPage1[i];`
152			`HTLBASID <= TLBASID[i];`
153			`HTLBG <= TLBG[i];`
154			`HTLBD <= TLBD[i];`
155			`HTLBValid <= TLBValid[i];`
156			`end`
157	48	robfinch	`else if (wTlbwi) begin`
158	30	robfinch	`TLBVirtPage[i] <= HTLBVirtPage;`
159			`TLBPhysPage0[i] <= HTLBPhysPage0;`
160			`TLBPhysPage1[i] <= HTLBPhysPage1;`
161			`TLBASID[i] <= HTLBASID;`
162			`TLBG[i] <= HTLBG;`
163			`TLBD[i] <= HTLBD;`
164			`TLBValid[i] <= HTLBValid;`
165			`end`
166	48	robfinch	`else if (wTlbwr) begin`
167	30	robfinch	`TLBVirtPage[i] <= HTLBVirtPage;`
168			`TLBPhysPage0[i] <= HTLBPhysPage0;`
169			`TLBPhysPage1[i] <= HTLBPhysPage1;`
170			`TLBASID[i] <= HTLBASID;`
171			`TLBG[i] <= HTLBG;`
172			`TLBD[i] <= HTLBD;`
173			`TLBValid[i] <= HTLBValid;`
174			`end`
175			`// Set the dirty bit on a store`
176			`if (m1IsStore)`
177			`if (!m1UnmappedDataArea & !q[3])`
178			`TLBD[{q[2:0],pea[15:13]}] <= 1'b1;`
179			`end`
180
181			`always @*`
182			`case(xregno)`
183			`TLBWired: dato = Wired;
184			`TLBIndex: dato = Index;
185			`TLBRandom: dato = Random;
186			`TLBPhysPage0: dato = {HTLBPhysPage0,13'd0};
187			`TLBPhysPage1: dato = {HTLBPhysPage1,13'd0};
188			`TLBVirtPage: dato = {HTLBVirtPage,13'd0};
189			`TLBPageMask: dato = {HTLBPageMask,13'd0};
190			`TLBASID: begin
191			`dato = 64'd0;`
192			`dato[0] = HTLBValid;`
193			`dato[1] = HTLBD;`
194			`dato[2] = HTLBG;`
195			`dato[15:8] = HTLBASID;`
196			`end`
197			`default: dato = 64'd0;`
198			`endcase`
199
200			`always @*`
201			`for (n = 0; n < 8; n = n + 1)`
202			`IMatch[n] = ((pc[63:13]\|TLBPageMask[{n[2:0],pc[15:13]}])==(TLBVirtPage[{n[2:0],pc[15:13]}]\|TLBPageMask[{n[2:0],pc[15:13]}])) &&`
203			`((TLBASID[{n,pc[15:13]}]==ASID) \|\| TLBG[{n,pc[15:13]}]) &&`
204			`TLBValid[{n,pc[15:13]}];`
205			`always @(IMatch)`
206			`if (IMatch[0]) m <= 4'd0;`
207			`else if (IMatch[1]) m <= 4'd1;`
208			`else if (IMatch[2]) m <= 4'd2;`
209			`else if (IMatch[3]) m <= 4'd3;`
210			`else if (IMatch[4]) m <= 4'd4;`
211			`else if (IMatch[5]) m <= 4'd5;`
212			`else if (IMatch[6]) m <= 4'd6;`
213			`else if (IMatch[7]) m <= 4'd7;`
214			`else m <= 4'd15;`
215
216			`wire ioddpage = \|({TLBPageMask[{m[2:0],pc[15:13]}]+19'd1,13'd0}&pc);`
217			`wire [63:13] IPFN = ioddpage ? TLBPhysPage1[{m[2:0],pc[15:13]}] : TLBPhysPage0[{m[2:0],pc[15:13]}];`
218
219			`assign ITLBMiss = !unmappedArea & m[3];`
220
221			assign ppc[63:13] = unmappedArea ? pc[63:13] : m[3] ? `TLBMissPage: IPFN;
222			`assign ppc[12:0] = pc[12:0];`
223
224			`always @(ea)`
225			`for (n = 0; n < 7; n = n + 1)`
226			`DMatch[n] = ((ea[63:13]\|TLBPageMask[{n,ea[15:13]}])==(TLBVirtPage[{n,ea[15:13]}]\|TLBPageMask[{n,ea[15:13]}])) &&`
227			`((TLBASID[{n,ea[15:13]}]==ASID) \|\| TLBG[{n,ea[15:13]}]) &&`
228			`TLBValid[{n,ea[15:13]}];`
229			`always @(DMatch)`
230			`if (DMatch[0]) q <= 4'd0;`
231			`else if (DMatch[1]) q <= 4'd1;`
232			`else if (DMatch[2]) q <= 4'd2;`
233			`else if (DMatch[3]) q <= 4'd3;`
234			`else if (DMatch[4]) q <= 4'd4;`
235			`else if (DMatch[5]) q <= 4'd5;`
236			`else if (DMatch[6]) q <= 4'd6;`
237			`else if (DMatch[7]) q <= 4'd7;`
238			`else q <= 4'd15;`
239
240			`wire doddpage = \|({TLBPageMask[{q[2:0],ea[15:13]}]+19'd1,13'd0}&ea);`
241			`wire [63:13] DPFN = doddpage ? TLBPhysPage1[{q[2:0],ea[15:13]}] : TLBPhysPage0[{q[2:0],ea[15:13]}];`
242
243			`assign DTLBMiss = !unmappedDataArea & q[3];`
244
245			assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[3] ? `TLBMissPage: DPFN;
246			`assign pea[12:0] = ea[12:0];`
247
248			`endmodule`
249

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