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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_addsub.v] - Blame information for rev 48

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1 31 robfinch
`include "Raptor64_opcodes.v"
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`timescale 1ns / 1ps
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//=============================================================================
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//        __
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//   \\__/ o\    (C) 2011,2012  Robert Finch
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//  
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//      Raptor64_addsub.v
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//  - addsub datapath operations
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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//=============================================================================
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//
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module Raptor64_addsub(xIR, a, b, imm, o);
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input [31:0] xIR;
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input [63:0] a;
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input [63:0] b;
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input [63:0] imm;
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output [63:0] o;
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reg [63:0] o;
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wire [6:0] xOpcode = xIR[31:25];
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wire [5:0] xFunc = xIR[5:0];
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wire [7:0] bcdaddo,bcdsubo;
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BCDAdd u1(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
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BCDSub u2(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
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always @(xOpcode,xFunc,a,b,imm,bcdaddo,bcdsubo)
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case (xOpcode)
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`RR:
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        case(xFunc)
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        `ADD:   o = a + b;
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        `ADDU:  o = a + b;
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        `SUB:   o = a - b;
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        `SUBU:  o = a - b;
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        `BCD_ADD:       o = bcdaddo;
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        `BCD_SUB:       o = bcdsubo;
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        default:        o = 64'd0;
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        endcase
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`INB,`INCH,`INH,`INW,`INCU,`INHU,`INBU,
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`OUTB,`OUTC,`OUTH,`OUTW,`OUTBC,
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`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LEA,`LF,`LFD,`LWR,
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`SW,`SH,`SC,`SB,`SF,`SFD,`SWC,
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`ADDI,`ADDUI:
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                o = a + imm;
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`SUBI:  o = a - imm;
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`SUBUI: o = a - imm;
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default:        o = 64'd0;
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endcase
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endmodule

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