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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_dcache_tagram.v] - Blame information for rev 48

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1 48 robfinch
`timescale 1ns / 1ps
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//=============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//  
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//      Raptor64_dcache_tagram.v
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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//=============================================================================
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//
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module Raptor64_dcache_tagram(wclk, we, adr, d, rclk, ea, tago);
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input wclk;
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input we;
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input [8:0] adr;
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input [49:0] d;
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input rclk;
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input [8:0] ea;
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output [49:0] tago;
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reg [49:0] ram [0:511];
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reg [8:0] radr;
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always @(posedge wclk)
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        if (we) ram[adr] <= d;
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always @(posedge rclk)
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        radr <= ea;
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assign tago = ram[radr];
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endmodule

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