OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_icache_ram.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 robfinch
`timescale 1ns / 1ps
2
//=============================================================================
3
//        __
4
//   \\__/ o\    (C) 2013  Robert Finch
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@opencores.org
7
//       ||
8
//  
9
//      Raptor64_icache_ram.v
10
//
11
//  
12
// This source file is free software: you can redistribute it and/or modify 
13
// it under the terms of the GNU Lesser General Public License as published 
14
// by the Free Software Foundation, either version 3 of the License, or     
15
// (at your option) any later version.                                      
16
//                                                                          
17
// This source file is distributed in the hope that it will be useful,      
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
20
// GNU General Public License for more details.                             
21
//                                                                          
22
// You should have received a copy of the GNU General Public License        
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
24
//                                                                          
25
//
26
//=============================================================================
27
//
28
module Raptor64_icache_ram(wclk, we, adr, d, rclk, pc, insn);
29
input wclk;
30
input we;
31
input [13:0] adr;
32
input [63:0] d;
33
input rclk;
34
input [13:0] pc;
35
output [31:0] insn;
36
 
37
reg [31:0] ramLo [0:2047];
38
reg [31:0] ramHi [0:2047];
39
reg [13:2] radr;
40
 
41
always @(posedge wclk)
42
        if (we) begin
43
                ramLo[adr[13:3]] <= d[31: 0];
44
                ramHi[adr[13:3]] <= d[63:32];
45
        end
46
 
47
always @(posedge rclk)
48
        radr <= pc[13:2];
49
 
50
assign insn = radr[2] ? ramHi[radr[13:3]] : ramLo[radr[13:3]];
51
 
52
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.