Subversion Repositories raptor64

`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2011-2013  Robert Finch, Stratford

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@opencores.org

//       ||

//

// Raptor64sc.v

//  - 64 bit CPU

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//                                                                          

// 15848 LUT's / 3591 ff's / 48.215 MHz

// 29 Block RAMs

// ============================================================================

//

//`define ADDRESS_RESERVATION   1

//`define FLOATING_POINT                1

//`define BTB                                   1

//`define TLB           1

//`define SIMD          1

`define SEGMENTATION    1

`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0

`define EX_NON                  9'd000

`define EX_TRAP                 9'd32   // Trap exception

`define EX_IRQ                  9'd448  // base IRQ interrupt

`define EX_DBZ                  9'd488  // divide by zero

`define EX_OFL                  9'd489  // overflow

`define EX_UNIMP_INSN   9'd495  // unimplemented instruction

`define EX_PRIV                 9'd496  // priviledge violation

`define EX_TLBD                 9'd506  // TLB exception - data

`define EX_TLBI                 9'd507  // TLB exception - ifetch

`define EX_DBERR                9'd508  // Bus Error - load or store or I/O

`define EX_IBERR                9'd509  // Bus Error - instruction fetch

`define EX_NMI                  9'd510  // non-maskable interrupt

`define EX_RST                  9'd511  // Reset

`include "Raptor64_opcodes.v"

module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, irq_no, bte_o, cti_o, bl_o, iocyc_o,

        cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr,

        advanceI, advanceR, advanceX, advanceM1, advanceM2, advanceW, advanceT

);

parameter IDLE = 5'd1;

parameter ICACT = 5'd2;

parameter ICACT1 = 5'd4;

parameter ICACT2 = 5'd5;

parameter DCIDLE = 5'd20;

parameter DCACT = 5'd21;

parameter AMSB = 31;

parameter RESET = 4'd0;

parameter RUN = 4'd1;

input rst_i;

input clk_i;

input nmi_i;

input irq_i;

input [8:0] irq_no;

output [1:0] bte_o;              // burst type

reg [1:0] bte_o;

output [2:0] cti_o;              // cycle type

reg [2:0] cti_o;

output [4:0] bl_o;               // burst length (non-WISHBONE)

reg [4:0] bl_o;

output iocyc_o;                 // I/O cycle is valid

reg iocyc_o;

output cyc_o;                   // cycle is valid

reg cyc_o;

output stb_o;                   // data strobe

reg stb_o;

input ack_i;                    // data transfer acknowledge

input err_i;                    // bus error

output we_o;                    // write enable

reg we_o;

output [7:0] sel_o;              // byte lane selects

reg [7:0] sel_o;

output rsv_o;                   // reserve the address (non-WISHBONE)

reg rsv_o;

output [63:0] adr_o;     // address

reg [63:0] adr_o;

input [63:0] dat_i;              // data input

output [63:0] dat_o;     // data output

reg [63:0] dat_o;

input sys_adv;

input [63:5] sys_adr;

output advanceI;

output advanceR;

output advanceX;

output advanceM1;

output advanceM2;

output advanceW;

output advanceT;

wire clk;

reg [3:0] state;

reg [5:0] fltctr;

wire fltdone = fltctr==6'd0;

reg bu_im;                      // interrupt mask

reg im1;                        // temporary interrupt mask for LM/SM

reg [7:0] ie_fuse;       // interrupt enable fuse

wire im = ~ie_fuse[7];

reg [1:0] rm;            // fp rounding mode

reg FXE;                        // fp exception enable

wire KernelMode;

wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,2'b00,10'b0};

reg [31:0] dIR,d1IR,xIR,m1IR,m2IR,wIR;

reg [31:0] ndIR;         // next dIR

reg [63:0] pc;                   // ipc

wire [63:0] pchistoric;

reg pccap;                              // flag 1=capture PC history

reg [63:0] ErrorEPC;

reg [63:0] EPC [0:15];    // Exception return address

reg [63:0] IPC [0:15];    // Interrupt return address

`ifdef SEGMENTATION

reg [63:16] CS [0:15];   // Code segment

reg [63:16] DS [0:15];   // Data segment

reg [63:16] SS [0:15];   // Stack segment

reg [63:16] ES [0:15];   // BSS segment

`endif

reg dStatusHWI,xStatusHWI,m1StatusHWI,m2StatusHWI;

reg dIm,xIm,m1Im,m2Im;

reg dNmi,xNmi,m1Nmi,m2Nmi,wNmi;

reg [15:0] StatusEXL;    // 1= context in exception state

reg [63:0] dpc,d1pc,xpc,m1pc,m2pc,wpc;           // PC's associated with instruction in pipeline

wire [63:0] rfoa,rfob,rfoc;              // register file outputs

wire [8:0] dRa,dRb,dRc;

reg [8:0] xRt,wRt,m1Rt,m2Rt,tRt; // target register

reg [63:0] ea;                   // effective data address

reg [4:0] cstate;                // cache state

reg dbranch_taken,xbranch_taken;        // flag: 1=branch taken

reg [63:0] mutex_gate;

reg [63:0] TBA;                  // Trap Base Address

reg [8:0] dextype,d1extype,xextype,m1extype,m2extype,wextype,textype;

reg [3:0] epat [0:255];

reg [7:0] eptr;

reg [3:0] dAXC,d1AXC,xAXC,m1AXC,m2AXC,wAXC;      // context active per pipeline stage

wire [3:0] AXC = (eptr==8'h00) ? 4'h0 : epat[eptr];

reg dtinit;                     // 1=data cache tags are being intialized

reg dcache_on;          // 1= data cache is enabled

wire [63:0] cdat;        // data cache output

reg [63:32] nonICacheSeg;

reg [1:0] FPC_rm;        // fp: rounding mode

reg FPC_SL;                     // result is negative (and non-zero)

reg FPC_SE;                     // result is zero

reg FPC_SG;                     // result is positive (and non-zero)

reg FPC_SI;                     // result is infinite or NaN

reg FPC_overx;

reg fp_iop;

reg fp_ovr;

reg fp_uf;

wire [31:0] FPC = {FPC_rm,1'b0,

                        9'd0,

                        FPC_SL,

                        FPC_SG,

                        FPC_SE,

                        FPC_SI,

                        16'd0

                        };

reg [63:0] wr_addr;

reg [31:0] insn;

reg clk_en;

reg cpu_clk_en;

reg StatusERL;          // 1= in error processing

//reg StatusEXL;                // 1= in exception processing

reg StatusHWI;          // 1= in interrupt processing

reg StatusUM;           // 1= user mode

reg [7:0] ASID;          // address space identifier (process ID)

integer n;

reg [63:13] BadVAddr;

reg [63:13] PageTableAddr;

reg [63:0] errorAddress;

wire [6:0] iOpcode = insn[31:25];

wire [6:0] iFunc = insn[6:0];

wire [5:0] iFunc6 = insn[5:0];

wire [6:0] dOpcode = dIR[31:25];

wire [6:0] dFunc = dIR[6:0];

wire [5:0] dFunc6 = dIR[5:0];

wire [6:0] xOpcode = xIR[31:25];

wire [6:0] xFunc = xIR[6:0];

wire [5:0] xFunc6 = xIR[5:0];

wire [4:0] xFunc5 = xIR[4:0];

wire [6:0] m1Opcode,m2Opcode,wOpcode;

assign m1Opcode = m1IR[31:25];

assign m2Opcode = m2IR[31:25];

assign wOpcode = wIR[31:25];

wire [6:0] m1Func,m2Func,wFunc;

assign m1Func = m1IR[6:0];

assign m2Func = m2IR[6:0];

assign wFunc = wIR[6:0];

wire [5:0] m1Func6 = m1Func[5:0];

wire [5:0] m2Func6 = m2Func[5:0];

wire [5:0] wFunc6 = wIR[5:0];

reg [63:0] m1Data,m2Data,wData,tData;

reg [63:0] m2Addr;

reg [63:0] tick;

reg [63:0] a,b,c,imm,m1b;

wire [1:0] scale = xIR[9:8];

wire [1:0] offset2 = xIR[7:6];

reg rsf;                                        // reserrved address flag

reg [63:5] resv_address;        // reserved address

reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;

reg xirqf;

wire advanceX_edge;

wire takb;

wire advanceI,advanceR,advanceR1,advanceX,advanceM1,advanceW,advanceT;  // Pipeline advance signals

reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;

reg dFip,d1Fip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;

reg cyc1;

reg LoadNOPs;

reg m1IsLoad,m1IsStore;

reg m2IsLoad,m2IsStore;

reg wIsStore;

reg m1IsOut,m1IsIn;

function [63:0] fnIncPC;

input [63:0] fpc;

begin

fnIncPC = fpc + 64'd4;

end

endfunction

function [7:0] fnSelect;

input [6:0] opcode;

input [2:0] addr;

case(opcode)

`LBU,`LB,`SB,`INB,`INBU,`OUTB:

        case(addr)

        3'b000: fnSelect = 8'b00000001;

        3'b001: fnSelect = 8'b00000010;

        3'b010: fnSelect = 8'b00000100;

        3'b011: fnSelect = 8'b00001000;

        3'b100: fnSelect = 8'b00010000;

        3'b101: fnSelect = 8'b00100000;

        3'b110: fnSelect = 8'b01000000;

        3'b111: fnSelect = 8'b10000000;

        endcase

`LC,`LCU,`SC,`INCH,`INCU,`OUTC:

        case(addr[2:1])

        2'b00:  fnSelect = 8'b00000011;

        2'b01:  fnSelect = 8'b00001100;

        2'b10:  fnSelect = 8'b00110000;

        2'b11:  fnSelect = 8'b11000000;

        endcase

`LHU,`LH,`SH,`LSH,`LF,`LFP,`SF,`SFP,`SSH,`INH,`INHU,`OUTH:

        case(addr[2])

        1'b0:   fnSelect = 8'b00001111;

        1'b1:   fnSelect = 8'b11110000;

        endcase

`LW,`LWR,`LM,`LFD,`LSW,`LP,`LFDP,

`SW,`SM,`SFD,`SSW,`SWC,`SP,`SFDP,`INW,`OUTW:

        fnSelect = 8'b11111111;

endcase

endfunction

reg [7:0] data8;

reg [15:0] data16;

reg [31:0] data32;

reg [63:0] data64;

always @(sel_o or dat_i)

        case(sel_o)

        8'b00000001:    data8 <= #1 dat_i[ 7: 0];

        8'b00000010:    data8 <= #1 dat_i[15: 8];

        8'b00000100:    data8 <= #1 dat_i[23:16];

        8'b00001000:    data8 <= #1 dat_i[31:24];

        8'b00010000:    data8 <= #1 dat_i[39:32];

        8'b00100000:    data8 <= #1 dat_i[47:40];

        8'b01000000:    data8 <= #1 dat_i[55:48];

        8'b10000000:    data8 <= #1 dat_i[63:56];

        default:        data8 <= 8'h00;

        endcase

always @(sel_o or dat_i)

        case(sel_o)

        8'b00000011:    data16 <= #1 dat_i[15: 0];

        8'b00001100:    data16 <= #1 dat_i[31:16];

        8'b00110000:    data16 <= #1 dat_i[47:32];

        8'b11000000:    data16 <= #1 dat_i[63:48];

        default:        data16 <= #1 16'hDEAD;

        endcase

always @(sel_o or dat_i)

        case(sel_o)

        8'b00001111:    data32 <= #1 dat_i[31: 0];

        8'b11110000:    data32 <= #1 dat_i[63:32];

        default:        data32 <= #1 32'hDEADDEAD;

        endcase

always @(sel_o or dat_i)

        data64 <= #1 dat_i;

assign KernelMode = StatusEXL[xAXC]|StatusHWI;

//wire iIsLSPair = iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP || 

//                              (iOpcode==`MEMNDX && (iFunc6==`SPX || iFunc6==`LPX || iFunc6==`SFPX || iFunc6==`LFPX || iFunc6==`SFDPX || iFunc6==`LFDPX));

//wire dIsLSPair = dOpcode==`SP || dOpcode==`LP || dOpcode==`SFP || dOpcode==`LFP || dOpcode==`SFDP || dOpcode==`LFDP ||

//                              (dOpcode==`MEMNDX && (dFunc6==`SPX || dFunc6==`LPX || dFunc6==`SFPX || dFunc6==`LFPX || dFunc6==`SFDPX || dFunc6==`LFDPX));

//wire xIsLSPair = xOpcode==`SP || xOpcode==`LP || xOpcode==`SFP || xOpcode==`LFP || xOpcode==`SFDP || xOpcode==`LFDP ||

//                               (xOpcode==`MEMNDX && (xFunc6==`SPX || xFunc6==`LPX || xFunc6==`SFPX || xFunc6==`LFPX || xFunc6==`SFDPX || xFunc6==`LFDPX));

//-----------------------------------------------------------------------------

// Segmentation

//

// If the upper nybble of the address is 'F' then segmentation is not applied.

// This allows for bootstrapping and operating system use. Also when in kernel

// mode the lowest 64k of memory is unsegmented to allow easier access to 

// operating system variables.

//

// Otherwise: the CS register is always in use for code addresses.

// Which segment is used for data addresses depends on the upper nybble of

// the address.

//-----------------------------------------------------------------------------

`ifdef SEGMENTATION

wire [63:0] spc;         // segmented PC

reg [63:0] sea;                  // segmented effective address

assign spc = pc[63:60]==4'hF ? pc : {CS[AXC][63:16] + pc[59:16],pc[15:0]};

always @(ea or KernelMode)

if (KernelMode && ea[63:16]==48'h0)

        sea <= ea;

else

        case(ea[63:60])

        4'hF:   sea <= ea;

        4'hE:   sea <= {SS[xAXC][63:16] + ea[59:16],ea[15:0]};

        4'hD:   sea <= {ES[xAXC][63:16] + ea[59:16],ea[15:0]};

        default:

                        sea <= {DS[xAXC][63:16] + ea[59:16],ea[15:0]};

        endcase

`else

wire [63:0] spc = pc;

wire [63:0] sea = ea;

`endif

//-----------------------------------------------------------------------------

// TLB

// The TLB contains 64 entries, that are 8 way set associative.

// The TLB is dual ported and shared between the instruction and data streams.

//-----------------------------------------------------------------------------

wire [63:0] ppc;

wire [63:0] pea;

wire [63:0] tlbo;

`ifdef TLB

wire [63:0] TLBVirtPage;

wire wTlbp = advanceW && wOpcode==`MISC && wFunc==`TLBP;

wire wTlbrd = advanceW && wOpcode==`MISC && wFunc==`TLBR;

wire wTlbwr = advanceW && wOpcode==`MISC && wFunc==`TLBWR;

wire wTlbwi = advanceW && wOpcode==`MISC && wFunc==`TLBWI;

wire wMtspr = advanceW && wOpcode==`R && wFunc==`MTSPR;

wire xTlbrd = advanceX && xOpcode==`MISC && xFunc==`TLBR;

wire xTlbwr = advanceX && xOpcode==`MISC && xFunc==`TLBWR;

wire xTlbwi = advanceX && xOpcode==`MISC && xFunc==`TLBWI;

wire ITLBMiss,DTLBMiss;

Raptor64_TLB u26

(

        .rst(rst_i),

        .clk(clk),

        .pc(spc),

        .ea(sea),

        .ppc(ppc),

        .pea(pea),

        .m1IsStore(advanceM1 && m1IsStore),

        .ASID(ASID),

        .wTlbp(wTlbp),

        .wTlbrd(wTlbrd),

        .wTlbwr(wTlbwr),

        .wTlbwi(wTlbwi),

        .xTlbrd(xTlbrd),

        .xTlbwr(xTlbwr),

        .xTlbwi(xTlbwi),

        .wr(wMtspr),

        .wregno(wIR[11:6]),

        .dati(wData),

        .xregno(xIR[11:6]),

        .dato(tlbo),

        .ITLBMiss(ITLBMiss),

        .DTLBMiss(DTLBMiss),

        .HTLBVirtPage(TLBVirtPage)

);

`else

assign ppc = spc;

assign pea = sea;

`endif

//-----------------------------------------------------------------------------

// Clock control

// - reset or NMI reenables the clock

// - this circuit must be under the clk_i domain

//-----------------------------------------------------------------------------

//

BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );

always @(posedge clk_i)

if (rst_i) begin

        cpu_clk_en <= 1'b1;

end

else begin

        if (nmi_i)

                cpu_clk_en <= 1'b1;

        else

                cpu_clk_en <= clk_en;

end

//assign clk = clk_i;

//-----------------------------------------------------------------------------

// Random number register:

//

// Uses George Marsaglia's multiply method.

//-----------------------------------------------------------------------------

reg [63:0] m_z;

reg [63:0] m_w;

reg [63:0] next_m_z;

reg [63:0] next_m_w;

always @(m_z or m_w)

begin

        next_m_z <= (36'd3696936969 * m_z[31:0]) + m_z[63:32];

        next_m_w <= (36'd1800018000 * m_w[31:0]) + m_w[63:32];

end

wire [63:0] rand = {m_z[31:0],32'd0} + m_w;

wire [10:0] bias = 11'h3FF;                              // bias amount (eg 127)

wire [10:0] xl = rand[62:53];

wire sgn = 1'b0;                                                                // floating point: always generate a positive number

wire [10:0] exp = xl > bias-1 ? bias-1 : xl;     // 2^-1 otherwise number could be over 1

wire [52:0] man = rand[52:0];                                     // a leading '1' will be assumed

wire [63:0] randfd = {sgn,exp,man};

reg [63:0] rando;

//-----------------------------------------------------------------------------

// Instruction Cache / Instruction buffer

// 

// On a bus error, the instruction cache / buffer is loaded with a SYSCALL 509

// instruction, which is a call to the bus error handler.

// Line size is 16 half-words (64 bytes). Total cache size is 16kB.

// 

//-----------------------------------------------------------------------------

//reg lfdir;

reg icaccess;

reg ICacheOn;

wire ibufrdy;

wire [31:0] insnbundle;

reg [31:0] insnbuf;

reg [63:0] ibufadr;

wire isICached = ppc[63:32]!=nonICacheSeg;

//wire isEncrypted = ppc[63:32]==encryptedArea;

wire ICacheAct = ICacheOn & isICached;

reg [31:0] insn1;

reg [31:0] insnkey;

reg [63:0] icadr;

// SYSCALL 509

wire syscall509 = 32'b0000000_00000_0000_11111110_10010111;

wire [63:0] bevect = {syscall509,syscall509};

Raptor64_icache_ram u1

(

        .wclk(clk),

        .we(icaccess & (ack_i|err_i)),

        .adr(icadr[13:0]),

        .d(err_i ? bevect : dat_i),

        .rclk(~clk),

        .pc(pc[13:0]),

        .insn(insnbundle)

);

always @(insnbundle or ICacheAct or insnbuf)

begin

        case(ICacheAct)

        1'b0:   insn1 <= insnbuf;

        1'b1:   insn1 <= insnbundle;

        endcase

end

// Decrypt the instruction set.

always @(insn1,insnkey)

        insn <= insn1 ^ insnkey;

reg [63:14] tmem [255:0];

reg [255:0] tvalid;

initial begin

        for (n=0; n < 256; n = n + 1)

                tmem[n] = 0;

        for (n=0; n < 256; n = n + 1)

                tvalid[n] = 0;

end

wire [64:14] tgout;

assign tgout = {tvalid[pc[13:6]],tmem[pc[13:6]]};

assign ihit = (tgout=={1'b1,ppc[63:14]});

assign ibufrdy = ibufadr[63:2]==ppc[63:2];

//-----------------------------------------------------------------------------

// Data Cache

// No-allocate on write

// Line size is 8 words (64 bytes). Total cache size is 32kB

//-----------------------------------------------------------------------------

reg dcaccess;

wire dhit;

wire [64:15] dtgout;

reg wrhit;

reg wr_dcache;

reg [14:0] dcadr;

// cache RAM 32Kb

Raptor64_dcache_ram u10

(

        .wclk(clk),

        .wr(1'b1),

        .sel(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00),

        .wadr(dcaccess ? dcadr[14:3] : adr_o[14:3]),

        .i(dcaccess ? dat_i : dat_o),

        .rclk(~clk),

        .radr(pea[14:3]),

        .o(cdat)