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`timescale 1ns / 1ps
//=============================================================================
//      (C) 2005-2012  Robert Finch
//      All rights reserved.
//      robfinch@Opencores.org
//
//      RaptorPIC.v
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
//              Encodes discrete interrupt request signals into four
//      bit code using a priority encoder.
//      
//      reg
//      0        - encoded request number (read only)
//                      This register contains the number identifying
//                      the current requester.
//                      the actual number is shifted left three times
//                      before being placed into this register so it may
//                      be used directly as an index in OS software. The
//                      index may be a mailbox id or index into a jump
//                      table as desired by the OS. If there is no
//                      active request, then this number will be 
//                      zero.
//      1       - request enable (read / write)
//                      this register contains request enable bits
//                      for each request line. 1 = request
//                      enabled, 0 = request disabled. On reset this
//                      register is set to zero (disable all ints).
//                      bit zero is specially reserved for nmi
//
//      2   - write only
//                      this register disables the interrupt indicated
//                      by the low order four bits of the input data
//                      
//      3       - write only
//                      this register enables the interrupt indicated
//                      by the low order four bits of the input data
//
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |WISHBONE Datasheet
//      |WISHBONE SoC Architecture Specification, Revision B.3
//      |
//      |Description:                                           Specifications:
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |General Description:                           simple programmable interrupt controller
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |Supported Cycles:                                      SLAVE,READ/WRITE
//      |                                                                       SLAVE,BLOCK READ/WRITE
//      |                                                                       SLAVE,RMW
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |Data port, size:                                       16 bit
//      |Data port, granularity:                        16 bit
//      |Data port, maximum operand size:       16 bit
//      |Data transfer ordering:                        Undefined
//      |Data transfer sequencing:                      Undefined
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |Clock frequency constraints:           none
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |Supported signal list and                      Signal Name             WISHBONE equiv.
//      |cross reference to equivalent          ack_o                           ACK_O
//      |WISHBONE signals                                       adr_i(2:1)                      ADR_I()
//      |                                                                       clk_i                           CLK_I
//      |                                                                       dat_i(15:0)                     DAT_I()
//      |                                                                       dat_o(15:0)                     DAT_O()
//      |                                                                       cyc_i                           CYC_I
//      |                                                                       stb_i                           STB_I
//      |                                                                       we_i                            WE_I
//      |
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//      |Special requirements:
//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
//
//      Spartan3-4
//      105 LUTs / 58 slices / 163MHz
//=============================================================================
 
module RaptorPIC
(
        input rst_i,            // reset
        input clk_i,            // system clock
        input cyc_i,            // cycle valid
        input stb_i,            // strobe
        output ack_o,           // transfer acknowledge
        input we_i,                     // write
        input [1:0] sel_i,       // byte select
        input [23:0] adr_i,      // address
        input [15:0] dat_i,
        output reg [15:0] dat_o,
        output vol_o,           // volatile register selected
        input i1, i2, i3, i4, i5, i6, i7,
                i8, i9, i10, i11, i12, i13, i14, i15,
        output irqo,    // normally connected to the processor irq
        input nmii,             // nmi input connected to nmi requester
        output nmio,    // normally connected to the nmi of cpu
        output [8:0] vecno
);
parameter pVECNO = 9'd448;
 
reg [15:0] ie;           // interrupt enable register
reg ack1;
reg [3:0] irqenc;
 
wire cs = cyc_i && stb_i && adr_i[23:4]==20'hDC_0FF;
assign vol_o = cs;
 
always @(posedge clk_i)
        ack1 <= cs;
assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;
 
// write registers      
always @(posedge clk_i)
        if (rst_i)
                ie <= 16'h0;
        else if (cs & we_i)
                case (adr_i[2:1])
                2'd0,2'd1:
                        begin
                                if (sel_i[0]) ie[ 7:0] <= dat_i[ 7:0];
                                if (sel_i[1]) ie[15:8] <= dat_i[15:8];
                        end
                2'd2,2'd3:
                        if (sel_i[0]) ie[dat_i[3:0]] <= adr_i[1];
                endcase
 
// read registers
always @(posedge clk_i)
begin
        if (irqenc!=4'd0)
                $display("PIC: %d",irqenc);
        if (cs)
                case (adr_i[2:1])
                2'd0:   dat_o <= {12'b0,irqenc};
                default:        dat_o <= ie;
                endcase
        else
                dat_o <= 16'h0000;
end
 
assign irqo = irqenc != 4'h0;
assign nmio = nmii & ie[0];
 
// irq requests are latched on every clock edge to prevent
// misreads
// nmi is not encoded
always @(posedge clk_i)
        case (1'b1)
        i1&ie[1]:               irqenc <= 4'd1;
        i2&ie[2]:               irqenc <= 4'd2;
        i3&ie[3]:               irqenc <= 4'd3;
        i4&ie[4]:               irqenc <= 4'd4;
        i5&ie[5]:               irqenc <= 4'd5;
        i6&ie[6]:               irqenc <= 4'd6;
        i7&ie[7]:               irqenc <= 4'd7;
        i8&ie[8]:               irqenc <= 4'd8;
        i9&ie[9]:               irqenc <= 4'd9;
        i10&ie[10]:     irqenc <= 4'd10;
        i11&ie[11]:             irqenc <= 4'd11;
        i12&ie[12]:             irqenc <= 4'd12;
        i13&ie[13]:             irqenc <= 4'd13;
        i14&ie[14]:             irqenc <= 4'd14;
        i15&ie[15]:             irqenc <= 4'd15;
        default:        irqenc <= 4'd0;
        endcase
 
assign vecno = pVECNO|irqenc;
 
endmodule

Line No.	Rev	Author	Line
1	33	robfinch	`timescale 1ns / 1ps
2	30	robfinch	`//=============================================================================`
3			`// (C) 2005-2012 Robert Finch`
4			`// All rights reserved.`
5			`// robfinch@Opencores.org`
6			`//`
7			`// RaptorPIC.v`
8			`//`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`//`
24			`// Encodes discrete interrupt request signals into four`
25			`// bit code using a priority encoder.`
26			`//`
27			`// reg`
28			`// 0 - encoded request number (read only)`
29			`// This register contains the number identifying`
30			`// the current requester.`
31			`// the actual number is shifted left three times`
32			`// before being placed into this register so it may`
33			`// be used directly as an index in OS software. The`
34			`// index may be a mailbox id or index into a jump`
35			`// table as desired by the OS. If there is no`
36			`// active request, then this number will be`
37			`// zero.`
38			`// 1 - request enable (read / write)`
39			`// this register contains request enable bits`
40			`// for each request line. 1 = request`
41			`// enabled, 0 = request disabled. On reset this`
42			`// register is set to zero (disable all ints).`
43			`// bit zero is specially reserved for nmi`
44			`//`
45			`// 2 - write only`
46			`// this register disables the interrupt indicated`
47			`// by the low order four bits of the input data`
48			`//`
49			`// 3 - write only`
50			`// this register enables the interrupt indicated`
51			`// by the low order four bits of the input data`
52			`//`
53			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
54			`// \|WISHBONE Datasheet`
55			`// \|WISHBONE SoC Architecture Specification, Revision B.3`
56			`// \|`
57			`// \|Description: Specifications:`
58			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
59			`// \|General Description: simple programmable interrupt controller`
60			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
61			`// \|Supported Cycles: SLAVE,READ/WRITE`
62			`// \| SLAVE,BLOCK READ/WRITE`
63			`// \| SLAVE,RMW`
64			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
65			`// \|Data port, size: 16 bit`
66			`// \|Data port, granularity: 16 bit`
67			`// \|Data port, maximum operand size: 16 bit`
68			`// \|Data transfer ordering: Undefined`
69			`// \|Data transfer sequencing: Undefined`
70			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
71			`// \|Clock frequency constraints: none`
72			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
73			`// \|Supported signal list and Signal Name WISHBONE equiv.`
74			`// \|cross reference to equivalent ack_o ACK_O`
75			`// \|WISHBONE signals adr_i(2:1) ADR_I()`
76			`// \| clk_i CLK_I`
77			`// \| dat_i(15:0) DAT_I()`
78			`// \| dat_o(15:0) DAT_O()`
79			`// \| cyc_i CYC_I`
80			`// \| stb_i STB_I`
81			`// \| we_i WE_I`
82			`// \|`
83			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
84			`// \|Special requirements:`
85			`// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
86			`//`
87			`// Spartan3-4`
88			`// 105 LUTs / 58 slices / 163MHz`
89			`//=============================================================================`
90
91			`module RaptorPIC`
92			`(`
93			`input rst_i, // reset`
94			`input clk_i, // system clock`
95			`input cyc_i, // cycle valid`
96			`input stb_i, // strobe`
97			`output ack_o, // transfer acknowledge`
98			`input we_i, // write`
99			`input [1:0] sel_i, // byte select`
100	33	robfinch	`input [23:0] adr_i, // address`
101	30	robfinch	`input [15:0] dat_i,`
102			`output reg [15:0] dat_o,`
103			`output vol_o, // volatile register selected`
104			`input i1, i2, i3, i4, i5, i6, i7,`
105			`i8, i9, i10, i11, i12, i13, i14, i15,`
106			`output irqo, // normally connected to the processor irq`
107			`input nmii, // nmi input connected to nmi requester`
108			`output nmio, // normally connected to the nmi of cpu`
109	50	robfinch	`output [8:0] vecno`
110	30	robfinch	`);`
111	50	robfinch	`parameter pVECNO = 9'd448;`
112	30	robfinch
113			`reg [15:0] ie; // interrupt enable register`
114			`reg ack1;`
115	50	robfinch	`reg [3:0] irqenc;`
116	30	robfinch
117	33	robfinch	`wire cs = cyc_i && stb_i && adr_i[23:4]==20'hDC_0FF;`
118	30	robfinch	`assign vol_o = cs;`
119
120			`always @(posedge clk_i)`
121	33	robfinch	`ack1 <= cs;`
122			`assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;`
123	30	robfinch
124			`// write registers`
125			`always @(posedge clk_i)`
126			`if (rst_i)`
127			`ie <= 16'h0;`
128			`else if (cs & we_i)`
129			`case (adr_i[2:1])`
130			`2'd0,2'd1:`
131			`begin`
132			`if (sel_i[0]) ie[ 7:0] <= dat_i[ 7:0];`
133			`if (sel_i[1]) ie[15:8] <= dat_i[15:8];`
134			`end`
135			`2'd2,2'd3:`
136			`if (sel_i[0]) ie[dat_i[3:0]] <= adr_i[1];`
137			`endcase`
138
139			`// read registers`
140			`always @(posedge clk_i)`
141	50	robfinch	`begin`
142			`if (irqenc!=4'd0)`
143			`$display("PIC: %d",irqenc);`
144	30	robfinch	`if (cs)`
145			`case (adr_i[2:1])`
146			`2'd0: dat_o <= {12'b0,irqenc};`
147			`default: dat_o <= ie;`
148			`endcase`
149			`else`
150			`dat_o <= 16'h0000;`
151	50	robfinch	`end`
152	30	robfinch
153			`assign irqo = irqenc != 4'h0;`
154			`assign nmio = nmii & ie[0];`
155
156			`// irq requests are latched on every clock edge to prevent`
157			`// misreads`
158			`// nmi is not encoded`
159			`always @(posedge clk_i)`
160			`case (1'b1)`
161			`i1&ie[1]: irqenc <= 4'd1;`
162			`i2&ie[2]: irqenc <= 4'd2;`
163			`i3&ie[3]: irqenc <= 4'd3;`
164			`i4&ie[4]: irqenc <= 4'd4;`
165			`i5&ie[5]: irqenc <= 4'd5;`
166			`i6&ie[6]: irqenc <= 4'd6;`
167			`i7&ie[7]: irqenc <= 4'd7;`
168			`i8&ie[8]: irqenc <= 4'd8;`
169			`i9&ie[9]: irqenc <= 4'd9;`
170			`i10&ie[10]: irqenc <= 4'd10;`
171			`i11&ie[11]: irqenc <= 4'd11;`
172			`i12&ie[12]: irqenc <= 4'd12;`
173			`i13&ie[13]: irqenc <= 4'd13;`
174			`i14&ie[14]: irqenc <= 4'd14;`
175			`i15&ie[15]: irqenc <= 4'd15;`
176			`default: irqenc <= 4'd0;`
177			`endcase`
178
179	50	robfinch	`assign vecno = pVECNO\|irqenc;`
180
181	30	robfinch	`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [RaptorPIC.v] - Blame information for rev 50