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aelmahmoud |
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/* This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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Email : semiconductors@varkongroup.com
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Tel : 1-732-447-8611
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*/
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/// module to calculate syndromes by doing GF_multiply
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// then add outputs of multipliaction
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module GF_mult_add_syndromes
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(
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input clk,
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input reset,
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input CE,
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input [7:0] ip1,ip2, /// power format
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input [2:0] count_in, // input number
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/// active high flag will be active for one clock when S of the RS_block is ready
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output reg S_Ready,
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output reg [7:0] S /// decimal format output syndromes value
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);
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reg [8:0] add_inputs;
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reg [7:0] out_GF_mult_0;
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reg [7:0] address_GF_dec;
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wire[7:0] out_GF_dec;
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reg [7:0] xor_reg0,xor_reg1,xor_reg2,xor_reg3,xor_reg4,xor_reg5,xor_reg6,xor_reg7;
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reg [7:0] cnt203_0,cnt203_1,cnt203_2,cnt203_3,cnt203_4,cnt203_5,cnt203_6,cnt203_7;
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reg CE1;
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//////////////////////GF_matrix_dec Rom //////////////////////////
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GF_matrix_dec rom_instant
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(
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.clk(clk),
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.re(CE || CE1),
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.address_read(address_GF_dec),
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.data_out(out_GF_dec)
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);
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//////////////////////////////////////////////////////////////////
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reg [7:0] ip1_0;
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reg [2:0] count_in0,count_in1,count_in2,count_in3;
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reg F; // to indicate if ip1_0 is FF or not
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////////////////////////GF_Multiply and accumilation //////////////
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always@(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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add_inputs<=0;
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out_GF_mult_0<=0;
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address_GF_dec<=0;
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xor_reg0<=0;xor_reg1<=0;xor_reg2<=0;xor_reg3<=0;
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xor_reg4<=0;xor_reg5<=0;xor_reg6<=0;xor_reg7<=0;
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cnt203_0<=204;cnt203_1<=204;cnt203_2<=204;cnt203_3<=204;
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cnt203_4<=204;cnt203_5<=204;cnt203_6<=204;cnt203_7<=204;
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S_Ready<=0;
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S<=0;
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F<=1;
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ip1_0<=8'hFF;
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count_in0<=0;count_in1<=0;count_in2<=0;count_in3<=0;
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CE1<=1;
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end
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else
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begin
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if(CE)
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begin
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CE1<=0;
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//======> 1st reg level---------------------------------
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ip1_0<=ip1;
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count_in0<=count_in;
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add_inputs <= ip1+ip2; //// 9 bits adding
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// ======> 2nd reg level -----------------------------------
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out_GF_mult_0<=add_inputs[7:0]+add_inputs[8];
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count_in1<=count_in0;
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if (&ip1_0)
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/// to make output take first value in GF_matrix_dec in this case ip1_0 == FF
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F<=1;
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else
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F<=0;
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// ======> 3rd reg level------------------------------------
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count_in2<=count_in1;
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address_GF_dec<= (F)? 8'h00:(&out_GF_mult_0)?8'h01:out_GF_mult_0+1;
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// ======> 4th reg level in the Rom latency---------------------
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count_in3<=count_in2;
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//////////////////////////////////////////////////////////////////
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case (count_in3)
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4: xor_reg4 <= xor_reg4 ^ out_GF_dec;
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5: xor_reg5 <= xor_reg5 ^ out_GF_dec;
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6: xor_reg6 <= xor_reg6 ^ out_GF_dec;
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7: xor_reg7 <= xor_reg7 ^ out_GF_dec;
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0: xor_reg0 <= xor_reg0 ^ out_GF_dec;
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1: xor_reg1 <= xor_reg1 ^ out_GF_dec;
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2: xor_reg2 <= xor_reg2 ^ out_GF_dec;
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default: xor_reg3 <= xor_reg3 ^ out_GF_dec;
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endcase
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///////////////////////////////////////////////////////////
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//// to make S_ready for only one clock
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if (S_Ready)
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begin
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S_Ready<=0;
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end
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//////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////
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case (count_in)
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///////////////////////////////////////////////////////
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0:
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begin
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if (cnt203_0 == 0)
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begin
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// start of output values , should be taken after this flag is high
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S_Ready <= 1;
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cnt203_0<=203;
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S<=xor_reg0;
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xor_reg0<=0;
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//// when input frame ends and the first byte of the next frame is
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//// entered the output syndromes is available
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end
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else
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cnt203_0 <=cnt203_0-1;
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end
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///////////////////////////////////////////////////////////////////////
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1:
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begin
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if (cnt203_1 == 0)
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begin
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cnt203_1<=203;
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S<=xor_reg1;
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xor_reg1<=0;
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//// when input frame ends and the first byte of the next
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////frame is entered the output syndromes is available
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end
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else
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cnt203_1<=cnt203_1-1;
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end
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///////////////////////////////////////////////////////////////
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2:
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begin
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if (cnt203_2 == 0)
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begin
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cnt203_2<=203;
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S<=xor_reg2;
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xor_reg2<=0;
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//// when input frame ends and the first byte
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//of the next frame is entered the output syndromes is available
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end
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else
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cnt203_2<=cnt203_2-1;
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end
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///////////////////////////////////////////////////////////////////////
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3:
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begin
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if (cnt203_3 == 0)
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begin
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cnt203_3<=203;
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S<=xor_reg3;
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xor_reg3<=0;
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//// when input frame ends and the first byte
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///of the next frame is entered the output syndromes is available
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end
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else
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cnt203_3<=cnt203_3-1;
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end
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//////////////////////////////////////////////////////////////////////
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4:
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begin
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if (cnt203_4 == 0)
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begin
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cnt203_4<=203;
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S<=xor_reg4;
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xor_reg4<=0;
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//// when input frame ends and the first byte of
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////the next frame is entered the output syndromes is available
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end
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else
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cnt203_4<=cnt203_4-1;
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end
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////////////////////////////////////////////////////////////////
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5:
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begin
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if (cnt203_5 == 0)
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begin
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cnt203_5<=203;
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S<=xor_reg5;
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xor_reg5<=0;
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//// when input frame ends and the first byte
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////of the next frame is entered the output syndromes is available
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end
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else
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cnt203_5<=cnt203_5-1;
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end
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//////////////////////////////////////////////////////////////
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begin
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if (cnt203_6 == 0)
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begin
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cnt203_6<=203;
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S<=xor_reg6;
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xor_reg6<=0;
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//// when input frame ends and the first byte of
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///the next frame is entered the output syndromes is available
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end
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else
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cnt203_6 <=cnt203_6-1;
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end
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///////////////////////////////////////////////////
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default:
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begin
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if (cnt203_7 == 0)
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begin
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cnt203_7<=203;
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S<=xor_reg7;
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xor_reg7<=0;
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//// when input frame ends and the first byte of
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///the next frame is entered the output syndromes is available
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end
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else
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cnt203_7 <=cnt203_7-1;
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end
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//////////////////////////////////////
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endcase
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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////////////////////////////////////////////////
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end // end if CE
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end //end else
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end // end always
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//////////////////////////////////////////////////////////////////
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endmodule
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