| 1 |
4 |
vk.semicon |
set_global_assignment -name FAMILY StratixIII
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| 2 |
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set_global_assignment -name DEVICE EP3SL150F1152C2
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| 3 |
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set_global_assignment -name TOP_LEVEL_ENTITY RS_dec
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| 4 |
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set_global_assignment -name VERILOG_FILE "../../rtl/transport_in2out.v"
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| 5 |
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set_global_assignment -name VERILOG_FILE "../../rtl/RS_dec.v"
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| 6 |
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set_global_assignment -name VERILOG_FILE "../../rtl/out_stage.v"
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| 7 |
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set_global_assignment -name VERILOG_FILE "../../rtl/Omega_Phy.v"
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| 8 |
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set_global_assignment -name VERILOG_FILE "../../rtl/lamda_roots.v"
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| 9 |
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set_global_assignment -name VERILOG_FILE "../../rtl/input_syndromes.v"
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| 10 |
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set_global_assignment -name VERILOG_FILE "../../rtl/GF_mult_add_syndromes.v"
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| 11 |
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set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_dec.v"
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| 12 |
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set_global_assignment -name VERILOG_FILE "../../rtl/GF_matrix_ascending_binary.v"
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| 13 |
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set_global_assignment -name VERILOG_FILE "../../rtl/error_correction.v"
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| 14 |
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set_global_assignment -name VERILOG_FILE "../../rtl/DP_RAM.v"
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| 15 |
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set_global_assignment -name VERILOG_FILE "../../rtl/BM_lamda.v"
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| 16 |
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set_global_assignment -name USER_LIBRARIES "../../rtl/;"
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| 17 |
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
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| 18 |
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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| 19 |
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
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| 20 |
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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| 21 |
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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| 22 |
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set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
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| 23 |
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set_global_assignment -name SMART_RECOMPILE ON
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| 24 |
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set_global_assignment -name ENABLE_DRC_SETTINGS ON
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| 25 |
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set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED
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| 26 |
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set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
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| 27 |
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set_global_assignment -name MUX_RESTRUCTURE OFF
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| 28 |
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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| 29 |
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
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| 30 |
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set_global_assignment -name IGNORE_LCELL_BUFFERS ON
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| 31 |
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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| 32 |
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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| 33 |
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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| 34 |
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set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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| 35 |
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set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
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| 36 |
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set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
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| 37 |
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set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
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| 38 |
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set_global_assignment -name DO_COMBINED_ANALYSIS ON
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| 39 |
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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| 40 |
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set_global_assignment -name SDC_FILE RS_dec.sdc
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| 41 |
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| 42 |
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| 43 |
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set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
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