Subversion Repositories rf68000

`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2008-2022  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//      rf68000.sv

//

//

// BSD 3-Clause License

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

//    list of conditions and the following disclaimer.

//

// 2. Redistributions in binary form must reproduce the above copyright notice,

//    this list of conditions and the following disclaimer in the documentation

//    and/or other materials provided with the distribution.

//

// 3. Neither the name of the copyright holder nor the names of its

//    contributors may be used to endorse or promote products derived from

//    this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//

// ============================================================================

//

// Uncomment the following to optimize for performance. Increases the core size.

//`define OPT_PERF    1'b1

`define BIG_ENDIAN      1'b1

//`define SUPPORT_RETRY 1'b1

`define SUPPORT_MUL     1'b1

`define SUPPORT_DIV     1'b1

`define SUPPORT_BCD     1'b1

//`define SUPPORT_010   1'b1

`define SUPPORT_BITPAIRS 1'b1

`define SUPPORT_DECFLT 1'b1

//`define HAS_MMU 1'b1

//`define SUPPORT_TASK  1'b1

//`define SUPPORT_B24   1'b1            // To support 23-bit branch displacements

`define TRUE        1'b1

`define FALSE       1'b0

`define HIGH        1'b1

`define LOW         1'b0

`define RESET_VECTOR    32'h00000400

`define CSR_CORENO    32'hFFFFFFE0

`define CSR_TICK        32'hFFFFFFE4

`define CSR_ICNT                                32'hFFFFFFE8

`define CSR_TASK        32'hFFFFFFFC

//`define SSP_VEC       9'd000

`define RESET_VEC       9'd001

`define BUSERR_VEC      9'd002

`define ADDRERR_VEC     9'd003

`define ILLEGAL_VEC     9'd004

`define DBZ_VEC         9'd005

`define CHK_VEC         9'd006

`define TRAPV_VEC       9'd007

`define PRIV_VEC        9'd008

`define TRACE_VEC       9'd009

`define LINE10_VEC      9'd010

`define LINE15_VEC      9'd011

`define UNINITINT_VEC   9'd015

// Vectors 24-31 for IRQ's

`define SPURIOUS_VEC            9'd024

`define IRQ_VEC         9'd024

// Vectors 32-46 for TRAPQ instruction

`define TRAP_VEC        9'd032

`define DISP_VEC                                9'd063

`define USER64          9'd064

//`define NMI_TRAP        9'h1FE

`define RESET_TASK      9'h000

`define LDB             16'b0001_xxx0xx_xxxxxx

`define LDH             16'b0010_xxx0xx_xxxxxx

`define LDW             16'b0011_xxx0xx_xxxxxx

`define STB             16'b0001_xxx1xx_xxxxxx

`define STH             16'b0010_xxx1xx_xxxxxx

`define STW             16'b0011_xxx1xx_xxxxxx

// DBcc also for Scc

`define DBRA    8'h50

`define DBSR    8'h51

`define DBHI    8'h52

`define DBLS    8'h53

`define DBHS    8'h54

`define DBLO    8'h55

`define DBNE    8'h56

`define DBEQ    8'h57

`define DBVC    8'h58

`define DBVS    8'h59

`define DBPL    8'h5A

`define DBMI    8'h5B

`define DBGE    8'h5C

`define DBLT    8'h5D

`define DBGT    8'h5E

`define DBLE    8'h5F

`define BRA             8'h60

`define BSR             8'h61

`define BHI             8'h62

`define BLS             8'h63

`define BHS             8'h64

`define BLO             8'h65

`define BNE             8'h66

`define BEQ             8'h67

`define BVC             8'h68

`define BVS             8'h69

`define BPL             8'h6A

`define BMI             8'h6B

`define BGE             8'h6C

`define BLT             8'h6D

`define BGT             8'h6E

`define BLE             8'h6F

// 12000 LUTs / 80MHz

// slices

// 1600 FF's

// 2 MULTS

// 8 BRAMs

module rf68000(coreno_i, clken_i, rst_i, rst_o, clk_i, nmi_i, ipl_i, vpa_i,

        lock_o, cyc_o, stb_o, ack_i, err_i, rty_i, we_o, sel_o, fc_o,

        asid_o, mmus_o, ios_o, iops_o, adr_o, dat_i, dat_o);

typedef enum logic [7:0] {

        IFETCH = 8'd1,

        DECODE,

        RETSTATE,

        FETCH_BYTE,

        FETCH_WORD,

        FETCH_LWORD,

        FETCH_LWORDa,

        STORE_BYTE,

        USTORE_BYTE,

        // 10

        STORE_WORD,

        STORE_LWORD,

        STORE_LWORDa,

        LFETCH_BYTE,

        FETCH_BRDISP,

        FETCH_BRDISPa,

        FETCH_IMM16,

        FETCH_IMM16a,

        FETCH_IMM32,

        FETCH_IMM32a,

        // 20

        FETCH_IMM32b,

        JSR,

        JMP,

        DBRA,

        ADDQ,

        ADDQ2,

        ADDI,

        ADDI2,

        ADDI3,

        ADDI4,

        // 30

        ADD,

        ADD1,

        DIV1,

        DIV2,

        STORE_IN_DEST,

        SHIFT,

        SHIFT1,

        BIT,

        BIT1,

        BIT2,

        // 40

        RTD1,

        RTD2,

        RTE1,

        RTE2,

        RTE3,

        RTE4,

        RTE5,

        RTE6,

        RTE7,

        RTE8,

        // 50

        RTE9,

        RTE10,

        RTE11,

        RTS1,

        RTS2,

        LINK,

        LINK1,

        LINK2,

        UNLNK,

        UNLNK2,

        // 60

        JMP_VECTOR,

        JMP_VECTOR2,

        JMP_VECTOR3,

        NEG,

        NEGX,

        NEGX1,

        NOT,

        TAS,

        LEA,

        LEA2,

        //70

        EXG1,

        CMP,

        CMP1,

        CMPA,

        CMPM,

        CMPM1,  // defunct

        AND,

        AND1,

        EOR,

        ANDI_CCR,

        // 80

        ANDI_CCR2,

        ANDI_SR,

        ANDI_SRX,

        EORI_CCR,

        EORI_CCR2,

        EORI_SR,

        EORI_SRX,

        ORI_CCR,

        ORI_CCR2,

        ORI_SR,

        //90

        ORI_SRX,

        FETCH_NOP_BYTE,

        FETCH_NOP_WORD,

        FETCH_NOP_LWORD,

        FETCH_IMM8,

        FETCH_IMM8a,

        FETCH_D32,

        FETCH_D32a,

        FETCH_D32b,

        FETCH_D16,

        //100

        FETCH_D16a,

        FETCH_NDX,

        FETCH_NDXa,

        MOVE2CCR,

        MOVE2SR,

        MOVE2SRX,

        TRAP,

        TRAP3,

        TRAP3a,

        TRAP3b,

        //110

        TRAP4,

        TRAP5,

        TRAP6,

        TRAP7,

        TRAP7a,

        TRAP8,

        TRAP9,

        TRAP10,

        TRAP20,

        TRAP21,

        // 120

        TRAP22,

        TRAP23,

        TRAP24,

        TRAP25,

        TRAP26,

        INTA,

        RETRY,

        RETRY2,

        TST,

        MUL,

        // 130

        MUL1,

        STOP,

        STOP1,

        RESET,

        RESET2,

        RESET3,

        RESET4,

        RESET5,

        PEA1,

        PEA2,

        // 140

        PEA3,

        BCD,

        BCD0,

        BCD1,

        BCD2,

        BCD3,

        BCD4,

        OR,

        INT,

        INT2,

        // 150

        INT3,

        INT4,

        MOVEM_Xn2D,

        MOVEM_Xn2D2,

        MOVEM_Xn2D3,

        MOVEM_Xn2D4,

        MOVEM_s2Xn,

        MOVEM_s2Xn2,

        MOVEM_s2Xn3,

        TASK1,

        // 160

        THREAD2,

        TASK3,

        TASK4,

        LDT1,

        LDT2,

        LDT3,

        SDT1,

        SDT2,

        SUB,

        SUB1,

        // 170

        MOVEP,

        MOVEP1,

        MOVEP2,

        MOVEP3,

        CHK,

        MOVERc2Rn,

        MOVERn2Rc,

        MOVERn2Rc2,

        MOVES,

        MOVES2,

        // 180

        MOVES3,

        ADDX,

        ADDX2,

        ADDX3,

        SUBX,

        SUBX2,

        SUBX3,

        MULU1,

        MULU2,

        MULU3,

        //190

        MULS1,

        MULS2,

        MULS3,

        BIN2BCD1,

        BIN2BCD2,

        BCD2BIN1,

        BCD2BIN2,

        BCD2BIN3,

        IFETCH2,

        FADD,

        // 200

        FCMP,

        FMUL1,

        FMUL2,

        FDIV1,

        FDIV2,

        FNEG,

        FMOVE,

        I2DF1,

        I2DF2,

        DF2I1,

        DF2I2,

        FTST,

        FBCC,

        FSCALE,

        FCOPYEXP,

        FETCH_HEXI1,

        FETCH_HEXI2,

        FETCH_HEXI3,

        FETCH_HEXI4,

        FETCH_NOP_HEXI,

        STORE_HEXI1,

        STORE_HEXI2,

        STORE_HEXI3,

        STORE_HEXI4,

        FMOVEM1,

        FETCH_IMM96,

        FETCH_IMM96b,

        FETCH_IMM96c,

        FETCH_IMM96d,

        CCHK,

        FSDATA2

} state_t;

typedef enum logic [4:0] {

        FU_NONE = 5'd0,

        FU_MUL,

        FU_TST, FU_ADDX, FU_SUBX,

        FU_CMP, FU_ADD, FU_SUB, FU_LOGIC, FU_ADDQ, FU_SUBQ,

        FU_ADDI, FU_ANDI_CCR, FU_ANDI_SR, FU_EORI_CCR,

        FU_ANDI_SRX, FU_EORI_SRX, FU_ORI_SRX, FU_MOVE2SRX,

        FU_EORI_SR, FU_ORI_CCR, FU_ORI_SR, FU_MOVE2CCR,

        FU_MOVE2SR

} flag_update_t;

parameter S = 1'b0;

parameter D = 1'b1;

input [31:0] coreno_i;

input clken_i;

input rst_i;

output reg rst_o;

input clk_i;

input nmi_i;

input vpa_i;

input [2:0] ipl_i;

output lock_o;

reg lock_o;

output cyc_o;

reg cyc_o;

output stb_o;

reg stb_o;

input ack_i;

input err_i;

input rty_i;

output we_o;

reg we_o;

output [3:0] sel_o;

reg [3:0] sel_o;

output [2:0] fc_o;

reg [2:0] fc_o;

output [7:0] asid_o;

output mmus_o;

output ios_o;

output iops_o;

output [31:0] adr_o;

reg [31:0] adr_o;

input [31:0] dat_i;

output [31:0] dat_o;

reg [31:0] dat_o;

wire DECFLT = coreno_i==32'd2;

reg em;                                                 // emulation mode

reg [15:0] ir;

reg [15:0] ir2;                 // second word for ir

reg ext_ir;

reg [31:0] icnt;

state_t state;

state_t rstate;

state_t state_stk1;

state_t state_stk2;

state_t state_stk3;

state_t state_stk4;

state_t state_stk5;

state_t sz_state;

flag_update_t flag_update;

reg [31:0] d0 = 'd0;

reg [31:0] d1 = 'd0;

reg [31:0] d2 = 'd0;

reg [31:0] d3 = 'd0;

reg [31:0] d4 = 'd0;

reg [31:0] d5 = 'd0;

reg [31:0] d6 = 'd0;

reg [31:0] d7 = 'd0;

reg [31:0] a0 = 'd0;

reg [31:0] a1 = 'd0;

reg [31:0] a2 = 'd0;

reg [31:0] a3 = 'd0;

reg [31:0] a4 = 'd0;

reg [31:0] a5 = 'd0;

reg [31:0] a6 = 'd0;

reg [31:0] sp = 'd0;

reg [95:0] fp0 = 'd0;

reg [95:0] fp1 = 'd0;

reg [95:0] fp2 = 'd0;

reg [95:0] fp3 = 'd0;

reg [95:0] fp4 = 'd0;

reg [95:0] fp5 = 'd0;

reg [95:0] fp6 = 'd0;

reg [95:0] fp7 = 'd0;

reg [31:0] d0i;

reg [31:0] d1i;

reg [31:0] d2i;

reg [31:0] d3i;

reg [31:0] d4i;

reg [31:0] d5i;

reg [31:0] d6i;

reg [31:0] d7i;

reg [31:0] a0i;

reg [31:0] a1i;

reg [31:0] a2i;

reg [31:0] a3i;

reg [31:0] a4i;

reg [31:0] a5i;

reg [31:0] a6i;

reg [31:0] spi;

reg [31:0] flagsi;

reg [31:0] pci;

wire [31:0] d0o;

wire [31:0] d1o;

wire [31:0] d2o;

wire [31:0] d3o;

wire [31:0] d4o;

wire [31:0] d5o;

wire [31:0] d6o;

wire [31:0] d7o;

wire [31:0] a0o;

wire [31:0] a1o;

wire [31:0] a2o;

wire [31:0] a3o;

wire [31:0] a4o;

wire [31:0] a5o;

wire [31:0] a6o;

wire [31:0] spo;

wire [31:0] flagso;

wire [31:0] pco;

reg cf,vf,nf,zf,xf,sf,tf;

reg [2:0] im;

reg [2:0] ccr57;

reg [1:0] sr1112;

reg sr14;

wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};

wire [31:0] srx = {sr};

reg fnf,fzf,fvf,fnanf;

wire finff = fvf;

reg [7:0] quotient_bits;

reg [2:0] quotient_bitshi;

reg [7:0] fpexc,fpaexc;

wire [31:0] fpsr = {1'b0,quotient_bitshi,fnf,fzf,fvf,fnanf,quotient_bits,fpexc,fpaexc};

reg [31:0] isr;

reg [3:0] ifmt;

reg [7:0] fpcnt;

reg [31:0] pc;

reg [31:0] opc;                 // pc for branch references

reg [31:0] fpiar;

reg [31:0] ssp,usp;

reg [31:0] disp;

reg [31:0] s,d,dd,imm,immx;

reg [31:0] bit2test;

reg wl;

reg ds;

reg [5:0] cnt;                          // shift count

reg [31:0] ea;                          // effective address

reg [31:0] vector;

reg [7:0] vecno;

reg [3:0] Rt;

wire [1:0] sz = ir[7:6];

reg dsix;

reg [2:0] mmm,mmmx,mmm_save='d0;

reg [2:0] rrr,rrrx;

reg [3:0] rrrr;

wire [2:0] MMM = ir[8:6];

wire [2:0] RRR = ir[11:9];

wire [2:0] QQQ = ir[11:9];

wire [2:0] DDD = ir[11:9];

wire [2:0] AAA = ir[11:9];

reg [2:0] FLTSRC;

reg [2:0] FLTDST;

reg MMMRRR;

wire Anabit;

wire [31:0] sp_dec = sp - 32'd2;

reg [31:0] rfoAn;

always_comb

case(rrr)

3'd0: rfoAn <= a0;

3'd1: rfoAn <= a1;

3'd2: rfoAn <= a2;

3'd3: rfoAn <= a3;

3'd4: rfoAn <= a4;

3'd5: rfoAn <= a5;

3'd6: rfoAn <= a6;

3'd7: rfoAn <= sp;

endcase

reg [31:0] rfoAna;

always_comb

case(AAA)

3'd0: rfoAna <= a0;

3'd1: rfoAna <= a1;

3'd2: rfoAna <= a2;

3'd3: rfoAna <= a3;

3'd4: rfoAna <= a4;

3'd5: rfoAna <= a5;

3'd6: rfoAna <= a6;

3'd7: rfoAna <= sp;

endcase

//wire [31:0] rfoAn =   rrr==3'b111 ? sp : regfile[{1'b1,rrr}];

reg [31:0] rfoDn;

always_comb

case(DDD)

3'd0:   rfoDn <= d0;

3'd1:   rfoDn <= d1;

3'd2:   rfoDn <= d2;

3'd3:   rfoDn <= d3;

3'd4:   rfoDn <= d4;

3'd5:   rfoDn <= d5;

3'd6:   rfoDn <= d6;

3'd7:   rfoDn <= d7;

endcase

reg [31:0] rfoDnn;

always_comb

case(rrr)

3'd0:   rfoDnn <= d0;

3'd1:   rfoDnn <= d1;

3'd2:   rfoDnn <= d2;

3'd3:   rfoDnn <= d3;

3'd4:   rfoDnn <= d4;

3'd5:   rfoDnn <= d5;

3'd6:   rfoDnn <= d6;

3'd7:   rfoDnn <= d7;

endcase

reg [31:0] rfob;

always_comb

case({mmm[0],rrr})

4'd0:   rfob <= d0;

4'd1:   rfob <= d1;

4'd2:   rfob <= d2;

4'd3:   rfob <= d3;

4'd4:   rfob <= d4;

4'd5:   rfob <= d5;

4'd6:   rfob <= d6;

4'd7:   rfob <= d7;

4'd8:   rfob <= a0;

4'd9:   rfob <= a1;

4'd10:  rfob <= a2;

4'd11:  rfob <= a3;

4'd12:  rfob <= a4;

4'd13:  rfob <= a5;

4'd14:  rfob <= a6;

4'd15:  rfob <= sp;

endcase

reg [31:0] rfoRnn;

always_comb

case(rrrr)

4'd0:   rfoRnn <= d0;

4'd1:   rfoRnn <= d1;

4'd2:   rfoRnn <= d2;

4'd3:   rfoRnn <= d3;

4'd4:   rfoRnn <= d4;

4'd5:   rfoRnn <= d5;

4'd6:   rfoRnn <= d6;

4'd7:   rfoRnn <= d7;

4'd8:   rfoRnn <= a0;

4'd9:   rfoRnn <= a1;

4'd10:  rfoRnn <= a2;

4'd11:  rfoRnn <= a3;

4'd12:  rfoRnn <= a4;

4'd13:  rfoRnn <= a5;

4'd14:  rfoRnn <= a6;

4'd15:  rfoRnn <= sp;

endcase

reg [95:0] rfoFpdst, rfoFpsrc;

`ifdef SUPPORT_DECFLT

always_comb

case(FLTDST)

3'd0:   rfoFpdst <= fp0;

3'd1:   rfoFpdst <= fp1;

3'd2:   rfoFpdst <= fp2;

3'd3:   rfoFpdst <= fp3;

3'd4:   rfoFpdst <= fp4;

3'd5:   rfoFpdst <= fp5;

3'd6:   rfoFpdst <= fp6;

3'd7:   rfoFpdst <= fp7;

endcase

always_comb

case(FLTSRC)

3'd0:   rfoFpsrc <= fp0;

3'd1:   rfoFpsrc <= fp1;

3'd2:   rfoFpsrc <= fp2;

3'd3:   rfoFpsrc <= fp3;

3'd4:   rfoFpsrc <= fp4;

3'd5:   rfoFpsrc <= fp5;

3'd6:   rfoFpsrc <= fp6;

3'd7:   rfoFpsrc <= fp7;

endcase

`endif

//wire [31:0] rfoDn = regfile[{1'b0,DDD}];

//wire [31:0] rfoAna = AAA==3'b111 ? sp : regfile[{1'b1,AAA}];

//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];

//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];

//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];

wire clk_g;

reg rfwrL,rfwrB,rfwrW;

reg rfwrF;

reg takb, ftakb;

reg [8:0] resB;

reg [16:0] resW;

reg [32:0] resL;

reg [95:0] resF;

reg [95:0] fps, fpd;

(* USE_DSP = "no" *)

reg [32:0] resL1,resL2;

reg [32:0] resMS1,resMS2,resMU1,resMU2;

reg [31:0] st_data;

wire [11:0] bcdaddo,bcdsubo,bcdnego;

wire bcdaddoc,bcdsuboc,bcdnegoc;

reg [31:0] bad_addr;

reg [15:0] mac_cycle_type;

reg prev_nmi;

reg pe_nmi;

reg is_nmi;

reg is_irq, is_trace, is_priv, is_illegal;

reg is_adr_err;

reg is_rst;

reg is_bus_err;

reg use_dfc, use_sfc;

reg [4:0] rst_cnt;

reg [2:0] shift_op;

reg rtr;

reg bsr;

reg lea;

reg fsub,fabs;

reg bcdsub, bcdneg;

reg fmovem;

reg [31:0] dati_buf;    // input data from bus error

reg [31:0] dato_buf;

// CSR's

reg [31:0] tick;        // FF0

reg [7:0] asid;         // 003

assign asid_o = asid;

reg [31:0] vbr;         // 801

reg [31:0] sfc;         // 000

reg [31:0] dfc;         // 001

reg [31:0] apc;

reg [7:0] cpl;

reg [31:0] tr;

reg [31:0] tcba;

reg [31:0] mmus, ios, iops;

reg [31:0] canary;

assign mmus_o = adr_o[31:20] == mmus[31:20];

assign iops_o = adr_o[31:16] == iops[31:16];

assign ios_o  = adr_o[31:20] == ios [31:20];

wire [16:0] lfsr_o;

lfsr17 ulfsr1

(

        .rst(rst_i),

        .clk(clk_g),

        .ce(1'b1),

        .cyc(1'b0),

        .o(lfsr_o)

);

/*

reg [31:0] cache_tag [0:7];

reg [15:0] cache_dat [0:7];

task tPushCache;

input [31:0] adr;

input [15:0] dat;

integer n;

begin

        for (n = 1; n < 8; n = n + 1) begin

                cache_tag[n] <= cache_tag[n-1];

                cache_dat[n] <= cache_dat[n-1];

        end

        cache_tag[0] <= adr;

        cache_dat[0] <= dat;

end

endtask

function fnInCache;

input [31:0] adr;

integer n;

begin

        fnInCache = 1'b0;

        for (n = 0; n < 8; n = n + 1) begin

                if (cache_tag[n]==adr) begin

                        fnInCache = 1'b1;

        end

end

endfunction

task tFindInCache;

input [31:0] adr;

output [15:0] dat;

integer n;

begin

        dat = 16'h4E71; // NOP

        for (n = 0; n < 8; n = n + 1) begin

                if (cache_tag[n]==adr) begin

                        dat = cache_dat[n];

                end

        end

end

endtask

*/

function [31:0] rbo;

input [31:0] w;

rbo = {w[7:0],w[15:8],w[23:16],w[31:24]};

endfunction

wire [7:0] dbin, sbin;

reg [9:0] bcdres;

wire dd_done;

wire [11:0] bcdreso;

BCDToBin ub2b1 (clk_g, d, dbin);

BCDToBin ub2b2 (clk_g, s, sbin);

DDBinToBCD #(.WID(10)) udd1

(

        .rst(rst_i),

        .clk(clk_g),

        .ld(state==BCD3),

        .bin(bcdres),

        .bcd(bcdreso),

        .done(dd_done)

);

reg [31:0] dd32in;

wire [39:0] dd32out;

wire dd32done;

DDBinToBCD #(.WID(32)) udd2

(

        .rst(rst_i),

        .clk(clk_g),

        .ld(state==BIN2BCD1),

        .bin(dd32in),

        .bcd(dd32out),

        .done(dd32done)

);

/*

BCDAdd u1

(

        .ci(xf),

        .a(s[7:0]),

        .b(d[7:0]),

        .o(bcdaddo),

        .c(bcdaddoc)

);

BCDSub u2

(

        .ci(xf),

        .a(d[7:0]),

        .b(s[7:0]),

        .o(bcdsubo),

        .c(bcdsuboc)

);

BCDSub u3

(

        .ci(xf),

        .a(8'h00),

        .b(d[7:0]),

        .o(bcdnego),

        .c(bcdnegoc)

);

*/

// These functions take the MSBs of the operands and results and return an

// overflow status.

// If the signs of the operands are the same, and the sign of the result does

// not match the operands sign.

function fnAddOverflow;

input r;

input a;

input b;

        fnAddOverflow = (r ^ b) & (1'b1 ^ a ^ b);

endfunction

// If the signs of the operands are different and sign of the result does not

// match the first operand.

function fnSubOverflow;

input r;

input a;

input b;

        fnSubOverflow = (r ^ a) & (a ^ b);

endfunction

reg divs;

wire dvdone;

wire dvByZr;

wire dvovf;

wire [31:0] divq;

wire [31:0] divr;