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-------------------------------------------------------------------------------
-- 
-- RapidIO IP Library Core
-- 
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
-- 
-- Description
-- Contains automatic test code to verify a RioWbBridge implementation.
-- 
-- To Do:
-- -
-- 
-- Author(s): 
-- - Magnus Rosenius, magro732@opencores.org 
-- 
-------------------------------------------------------------------------------
-- 
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
-- 
-- This source file may be used and distributed without 
-- restriction provided that this copyright statement is not 
-- removed from the file and that any derivative work contains 
-- the original copyright notice and the associated disclaimer. 
-- 
-- This source file is free software; you can redistribute it 
-- and/or modify it under the terms of the GNU Lesser General 
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any 
-- later version. 
-- 
-- This source is distributed in the hope that it will be 
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-- PURPOSE. See the GNU Lesser General Public License for more 
-- details. 
-- 
-- You should have received a copy of the GNU Lesser General 
-- Public License along with this source; if not, download it 
-- from http://www.opencores.org/lgpl.shtml 
-- 
-------------------------------------------------------------------------------
 
 
-- REMARK: Move the testport package and entities to a seperate file.
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.rio_common.all;
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
package TestPortPackage is
  constant ADDRESS_WIDTH : natural := 31;
  constant DATA_SIZE_MAX : natural := 32;
 
  type TestPortMessageWishbone is record
    writeAccess : boolean;
    address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    byteSelect : std_logic_vector(7 downto 0);
    length : natural range 1 to DATA_SIZE_MAX;
    data : DoublewordArray(0 to DATA_SIZE_MAX-1);
    latency : natural;
  end record;
 
  type TestPortMessageSymbol is record
    symbolType : std_logic_vector(1 downto 0);
    symbolContent : std_logic_vector(31 downto 0);
    ignoreIdle : boolean;
  end record;
 
  type TestPortMessagePacketBuffer is record
    frame : RioFrame;
    willAbort : boolean;
  end record;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  component TestPortWishbone is
    port(
      clk : in std_logic;
      areset_n : in std_logic;
 
      messageEmpty_o : out std_logic;
      messageWrite_i : in std_logic;
      message_i : in TestPortMessageWishbone;
      messageAck_o : out std_logic;
 
      cyc_i : in std_logic;
      stb_i : in std_logic;
      we_i : in std_logic;
      adr_i : in std_logic_vector(30 downto 0);
      sel_i : in std_logic_vector(7 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      err_o : out std_logic;
      ack_o : out std_logic);
  end component;
 
  component TestPortPacketBuffer is
    port(
      clk : in std_logic;
      areset_n : in std_logic;
 
      readEmpty_o : out std_logic;
      readWrite_i : in std_logic;
      readMessage_i : in TestPortMessagePacketBuffer;
      readAck_o : out std_logic;
 
      writeEmpty_o : out std_logic;
      writeWrite_i : in std_logic;
      writeMessage_i : in TestPortMessagePacketBuffer;
      writeAck_o : out std_logic;
 
      readFrameEmpty_o : out std_logic;
      readFrame_i : in std_logic;
      readFrameRestart_i : in std_logic;
      readFrameAborted_o : out std_logic;
      readWindowEmpty_o : out std_logic;
      readWindowReset_i : in std_logic;
      readWindowNext_i : in std_logic;
      readContentEmpty_o : out std_logic;
      readContent_i : in std_logic;
      readContentEnd_o : out std_logic;
      readContentData_o : out std_logic_vector(31 downto 0);
 
      writeFrame_i : in std_logic;
      writeFrameAbort_i : in std_logic;
      writeContent_i : in std_logic;
      writeContentData_i : in std_logic_vector(31 downto 0));
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortWishboneWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessageWishbone;
    signal ackSignal : in std_logic;
    constant writeAccess : in boolean;
    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant byteSelect : in std_logic_vector(7 downto 0);
    constant length : in natural range 1 to DATA_SIZE_MAX;
    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
    constant latency : natural := 0);
 
  procedure TestPortPacketBufferWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessagePacketBuffer;
    signal ackSignal : in std_logic;
    constant frame : in RioFrame;
    constant willAbort : boolean := false);
 
end package;
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
package body TestPortPackage is
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortWishboneWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessageWishbone;
    signal ackSignal : in std_logic;
    constant writeAccess : in boolean;
    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant byteSelect : in std_logic_vector(7 downto 0);
    constant length : in natural range 1 to DATA_SIZE_MAX;
    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
    constant latency : natural := 0) is
  begin
    writeSignal <= '1';
    messageSignal.writeAccess <= writeAccess;
    messageSignal.address <= address;
    messageSignal.byteSelect <= byteSelect;
    messageSignal.length <= length;
    messageSignal.data <= data;
    messageSignal.latency <= latency;
    wait until ackSignal = '1';
    writeSignal <= '0';
    wait until ackSignal = '0';
  end procedure;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  procedure TestPortPacketBufferWrite(
    signal writeSignal : out std_logic;
    signal messageSignal : out TestPortMessagePacketBuffer;
    signal ackSignal : in std_logic;
    constant frame : in RioFrame;
    constant willAbort : boolean := false) is
  begin
    writeSignal <= '1';
    messageSignal.frame <= frame;
    messageSignal.willAbort <= willAbort;
    wait until ackSignal = '1';
    writeSignal <= '0';
    wait until ackSignal = '0';
  end procedure;
 
end package body;
 
 
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
entity TestPortPacketBuffer is
  port(
    clk : in std_logic;
    areset_n : in std_logic;
 
    readEmpty_o : out std_logic;
    readWrite_i : in std_logic;
    readMessage_i : in TestPortMessagePacketBuffer;
    readAck_o : out std_logic;
 
    writeEmpty_o : out std_logic;
    writeWrite_i : in std_logic;
    writeMessage_i : in TestPortMessagePacketBuffer;
    writeAck_o : out std_logic;
 
    readFrameEmpty_o : out std_logic;
    readFrame_i : in std_logic;
    readFrameRestart_i : in std_logic;
    readFrameAborted_o : out std_logic;
    readWindowEmpty_o : out std_logic;
    readWindowReset_i : in std_logic;
    readWindowNext_i : in std_logic;
    readContentEmpty_o : out std_logic;
    readContent_i : in std_logic;
    readContentEnd_o : out std_logic;
    readContentData_o : out std_logic_vector(31 downto 0);
 
    -- writeFrameFull_o is missing yes, but you can control it from the testbench directly
    -- instead.
    writeFrame_i : in std_logic;
    writeFrameAbort_i : in std_logic;
    writeContent_i : in std_logic;
    writeContentData_i : in std_logic_vector(31 downto 0));
end entity;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is
  constant QUEUE_SIZE : natural := 63;
  type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;
 
  function QueueIndexInc(constant i : natural) return natural is
    variable returnValue : natural;
  begin
    if(i = QUEUE_SIZE) then
      returnValue := 0;
    else
      returnValue := i + 1;
    end if;
    return returnValue;
  end function;
 
begin
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Reader: process
    variable frameQueue : QueueArray(0 to QUEUE_SIZE);
    variable front, back, window : natural range 0 to QUEUE_SIZE;
    variable frameIndex : natural;
  begin
    wait until areset_n = '1';
 
    readFrameEmpty_o <= '1';
    readFrameAborted_o <= '0';
    readWindowEmpty_o <= '1';
    readContentEmpty_o <= '1';
    readContentEnd_o <= '0';
    readContentData_o <= (others=>'0');
 
    front := 0;
    back := 0;
    window := 0;
    frameIndex := 0;
    readEmpty_o <= '1';
    readAck_o <= '0';
 
    loop
      wait until clk = '1' or readWrite_i = '1';
 
      if (clk'event) then
        if (readFrame_i = '1') then
          if (back /= front) then
            back := QueueIndexInc(back);
          else
            TestError("READ:BACK:reading when no frame is present");
          end if;
        end if;
 
        if (readFrameRestart_i = '1') then
          frameIndex := 0;
        end if;
 
        if (readWindowReset_i = '1') then
          window := back;
          frameIndex := 0;
        end if;
 
        if (readWindowNext_i = '1') then
          if (window /= front) then
            window := QueueIndexInc(window);
            frameIndex := 0;
          else
            TestError("READ:WINDOW:reading when no frame is present");
          end if;
        end if;
 
        if (readContent_i = '1') then
          if (back /= front) then
            if (frameIndex < frameQueue(window).frame.length) then
              readContentData_o <= frameQueue(window).frame.payload(frameIndex);
              frameIndex := frameIndex + 1;
              if (frameIndex = frameQueue(window).frame.length) then
                readContentEnd_o <= '1';
              else
                readContentEnd_o <= '0';
              end if;
            else
              TestError("READ:CONTENT:reading when frame has ended");
            end if;
          else
            TestError("READ:CONTENT:reading when no frame is present");
          end if;
        end if;
 
        if (front = back) then
          readFrameEmpty_o <= '1';
        else
          readFrameEmpty_o <= '0';
        end if;
 
        if (front = window) then
          readWindowEmpty_o <= '1';
          readContentEmpty_o <= '1';
        else
          readWindowEmpty_o <= '0';
          if (frameIndex /= frameQueue(window).frame.length) then
            readContentEmpty_o <= '0';
          else
            readContentEmpty_o <= '1';
          end if;
        end if;
 
        if (front = back) then
          readEmpty_o <= '1';
        else
          readEmpty_o <= '0';
        end if;
      elsif (readWrite_i'event) then
        frameQueue(front) := readMessage_i;
        front := QueueIndexInc(front);
 
        readEmpty_o <= '0';
        readAck_o <= '1';
        wait until readWrite_i = '0';
        readAck_o <= '0';
      end if;
    end loop;
  end process;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Writer: process
    variable frameQueue : QueueArray(0 to QUEUE_SIZE);
    variable front, back : natural range 0 to QUEUE_SIZE;
    variable frameIndex : natural range 0 to 69;
  begin
    wait until areset_n = '1';
 
    writeEmpty_o <= '1';
    writeAck_o <= '0';
 
    front := 0;
    back := 0;
    frameIndex := 0;
 
    loop
      wait until clk = '1' or writeWrite_i = '1';
 
      if (clk'event) then
 
        if (writeFrame_i = '1') then
          if (frameIndex = 0) then
            TestError("WRITE:Empty frame written.");
          end if;
          if (frameIndex /= frameQueue(back).frame.length) then
            TestError("WRITE:Frame with unmatching length was written.");
          end if;
          if (back /= front) then
            back := QueueIndexInc(back);
          else
            TestError("WRITE:Unexpected frame written.");
          end if;
          frameIndex := 0;
        end if;
 
        if (writeFrameAbort_i = '1') then
          if (back /= front) then
            if (frameQueue(back).willAbort) then
              TestCompare(frameIndex,
                          frameQueue(back).frame.length,
                          "frameIndex abort");
              back := QueueIndexInc(back);
            else
              TestError("WRITE:Not expecting this frame to abort.");
            end if;
          end if;
          frameIndex := 0;
        end if;
 
        if (writeContent_i = '1') then
          if (frameIndex < frameQueue(back).frame.length) then
            TestCompare(writeContentData_i,
                        frameQueue(back).frame.payload(frameIndex),
                        "frame content");
            frameIndex := frameIndex + 1;
          else
            TestError("WRITE:Receiving more frame content than expected.");
          end if;
        end if;
 
        if (front = back) then
          writeEmpty_o <= '1';
        else
          writeEmpty_o <= '0';
        end if;
      elsif (writeWrite_i'event) then
        frameQueue(front) := writeMessage_i;
        front := QueueIndexInc(front);
 
        writeEmpty_o <= '0';
        writeAck_o <= '1';
        wait until writeWrite_i = '0';
        writeAck_o <= '0';
      end if;
    end loop;
  end process;
 
end architecture;
 
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
entity TestPortWishbone is
  port(
    clk : in std_logic;
    areset_n : in std_logic;
 
    messageEmpty_o : out std_logic;
    messageWrite_i : in std_logic;
    message_i : in TestPortMessageWishbone;
    messageAck_o : out std_logic;
 
    cyc_i : in std_logic;
    stb_i : in std_logic;
    we_i : in std_logic;
    adr_i : in std_logic_vector(30 downto 0);
    sel_i : in std_logic_vector(7 downto 0);
    dat_i : in std_logic_vector(63 downto 0);
    dat_o : out std_logic_vector(63 downto 0);
    err_o : out std_logic;
    ack_o : out std_logic);
end entity;
 
 
-------------------------------------------------------------------------------
-- 
-------------------------------------------------------------------------------
architecture TestPortWishboneImpl of TestPortWishbone is
  constant QUEUE_SIZE : natural := 63;
  type QueueArray is array (natural range <>) of TestPortMessageWishbone;
 
  function QueueIndexInc(constant i : natural) return natural is
    variable returnValue : natural;
  begin
    if(i = QUEUE_SIZE) then
      returnValue := 0;
    else
      returnValue := i + 1;
    end if;
    return returnValue;
  end function;
 
begin
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
  Slave: process
    variable queue : QueueArray(0 to QUEUE_SIZE);
    variable front, back : natural range 0 to QUEUE_SIZE;
    variable cyclePosition : natural;
    variable latencyCounter : natural;
  begin
    wait until areset_n = '1';
 
    messageEmpty_o <= '1';
    messageAck_o <= '0';
 
    dat_o <= (others=>'U');
    err_o <= '0';
    ack_o <= '0';
 
    front := 0;
    back := 0;
    cyclePosition := 0;
    latencyCounter := 0;
 
    loop
      wait until clk = '1' or messageWrite_i = '1';
 
      if (clk'event) then
        if (cyc_i = '1') then
          if (front /= back) then
            if (cyclePosition < queue(back).length) then
              TestCompare(stb_i, '1', "stb_i");
              if (queue(back).writeAccess) then
                TestCompare(we_i, '1', "we_i");
              else
                TestCompare(we_i, '0', "we_i");
              end if;
              -- REMARK: Add this...
              --TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");
              TestCompare(sel_i, queue(back).byteSelect, "sel_i");
              if (queue(back).writeAccess) then
                TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
              end if;
 
              if (latencyCounter = queue(back).latency) then
                dat_o <= queue(back).data(cyclePosition);
                ack_o <= '1';
                latencyCounter := 0;
                cyclePosition := cyclePosition + 1;
              else
                dat_o <= (others=>'U');
                ack_o <= '0';
                latencyCounter := latencyCounter + 1;
              end if;
            else
              back := QueueIndexInc(back);
              cyclePosition := 0;
              latencyCounter := 0;
              dat_o <= (others=>'U');
              ack_o <= '0';
            end if;
          else
            TestError("Unexpected access.");
          end if;
        else
          if (cyclePosition /= 0) or (latencyCounter /= 0) then
            TestError("Cycle unexpectedly aborted.");
            cyclePosition := 0;
            latencyCounter := 0;
          end if;
          TestCompare(stb_i, '0', "stb_i");
        end if;
 
        if (front = back) then
          messageEmpty_o <= '1';
        else
          messageEmpty_o <= '0';
        end if;
      elsif (messageWrite_i'event) then
        queue(front) := message_i;
        front := QueueIndexInc(front);
 
        messageEmpty_o <= '0';
        messageAck_o <= '1';
        wait until messageWrite_i = '0';
        messageAck_o <= '0';
      end if;
    end loop;
  end process;
 
end architecture;
 
 
-------------------------------------------------------------------------------
-- TestRioWbBridge.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- Entity for TestRioWbBridge.
-------------------------------------------------------------------------------
entity TestRioWbBridge is
end entity;
 
 
-------------------------------------------------------------------------------
-- Architecture for TestRioWbBridge.
-------------------------------------------------------------------------------
architecture TestRioWbBridgeImpl of TestRioWbBridge is
 
  component RioWbBridge is
    generic(
      EXTENDED_ADDRESS : natural range 0 to 2 := 0;
      DEVICE_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_REV : std_logic_vector(31 downto 0);
      ASSY_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_REV : std_logic_vector(15 downto 0));
    port(
      clk : in std_logic;
      areset_n : in std_logic;
      enable : in std_logic;
 
      readFrameEmpty_i : in std_logic;
      readFrame_o : out std_logic;
      readContent_o : out std_logic;
      readContentEnd_i : in std_logic;
      readContentData_i : in std_logic_vector(31 downto 0);
      writeFrameFull_i : in std_logic;
      writeFrame_o : out std_logic;
      writeFrameAbort_o : out std_logic;
      writeContent_o : out std_logic;
      writeContentData_o : out std_logic_vector(31 downto 0);
 
      cyc_o : out std_logic;
      stb_o : out std_logic;
      we_o : out std_logic;
      adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
      sel_o : out std_logic_vector(7 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      err_i : in std_logic;
      ack_i : in std_logic);
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  signal clk : std_logic;
  signal areset_n : std_logic;
  signal enable : std_logic;
 
  signal writeFrameFull : std_logic;
  signal writeFrame : std_logic;
  signal writeFrameAbort : std_logic;
  signal writeContent : std_logic;
  signal writeContentData : std_logic_vector(31 downto 0);
 
  signal readFrameEmpty : std_logic;
  signal readFrame : std_logic;
  signal readFrameRestart : std_logic;
  signal readFrameAborted : std_logic;
  signal readContentEmpty : std_logic;
  signal readContent : std_logic;
  signal readContentEnd : std_logic;
  signal readContentData : std_logic_vector(31 downto 0);
 
  signal wbCyc : std_logic;
  signal wbStb : std_logic;
  signal wbWe : std_logic;
  signal wbAdr : std_logic_vector(30 downto 0);
  signal wbSel : std_logic_vector(7 downto 0);
  signal wbDatWrite : std_logic_vector(63 downto 0);
  signal wbDatRead : std_logic_vector(63 downto 0);
  signal wbAck : std_logic;
  signal wbErr : std_logic;
 
  signal outboundEmpty : std_logic;
  signal outboundWrite : std_logic;
  signal outboundMessage : TestPortMessagePacketBuffer;
  signal outboundAck : std_logic;
 
  signal inboundEmpty : std_logic;
  signal inboundWrite : std_logic;
  signal inboundMessage : TestPortMessagePacketBuffer;
  signal inboundAck : std_logic;
 
  signal wbMessageEmpty : std_logic;
  signal wbMessageWrite : std_logic;
  signal wbMessage : TestPortMessageWishbone;
  signal wbMessageAck : std_logic;
 
begin
 
  -----------------------------------------------------------------------------
  -- Clock generation.
  -----------------------------------------------------------------------------
  ClockGenerator: process
  begin
    clk <= '0';
    wait for 20 ns;
    clk <= '1';
    wait for 20 ns;
  end process;
 
 
  -----------------------------------------------------------------------------
  -- Serial port emulator.
  -----------------------------------------------------------------------------
  TestDriver: process
 
    -----------------------------------------------------------------------------
    -- Procedures to handle outbound and inbound packets.
    -----------------------------------------------------------------------------
    procedure OutboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,
                                frame, false);
    end procedure;
 
    procedure InboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,
                                frame, false);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- Procedure to handle wishbone accesses.
    ---------------------------------------------------------------------------
    procedure SetSlaveAccess(constant writeAccess : in boolean;
                             constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
                             constant byteSelect : in std_logic_vector(7 downto 0);
                             constant length : in natural range 1 to DATA_SIZE_MAX;
                             constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
                             constant latency : natural := 1) is
    begin
      TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                            writeAccess, address, byteSelect, length, data, latency);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- 
    ---------------------------------------------------------------------------
    function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return natural is
    begin
      case rdsize is
        when "0000" | "0001" | "0010" | "0011" =>
          return 1;
        when "0100" | "0110" =>
          return 1;
        when "0101" =>
          return 1;
        when "1000" =>
          return 1;
        when "0111" =>
          return 1;
        when "1001" =>
          return 1;
        when "1010" =>
          return 1;
        when "1011" =>
          if (wdptr = '0') then
            return 1;
          else
            return 2;
          end if;
        when "1100" =>
          if (wdptr = '0') then
            return 4;
          else
            return 8;
          end if;
        when "1101" =>
          if (wdptr = '0') then
            return 12;
          else
            return 16;
          end if;
        when "1110" =>
          if (wdptr = '0') then
            return 20;
          else
            return 24;
          end if;
        when "1111" =>
          if (wdptr = '0') then
            return 28;
          else
            return 32;
          end if;
        when others =>
          return 0;
      end case;
    end function;
 
    function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return std_logic_vector is
    begin
      case rdsize is
        when "0000" =>
          if (wdptr = '0') then
            return "10000000";
          else
            return "00001000";
          end if;
        when "0001" =>
          if (wdptr = '0') then
            return "01000000";
          else
            return "00000100";
          end if;
        when "0010" =>
          if (wdptr = '0') then
            return "00100000";
          else
            return "00000010";
          end if;
        when "0011" =>
          if (wdptr = '0') then
            return "00010000";
          else
            return "00000001";
          end if;
        when "0100" =>
          if (wdptr = '0') then
            return "11000000";
          else
            return "00001100";
          end if;
        when "0110" =>
          if (wdptr = '0') then
            return "00110000";
          else
            return "00000011";
          end if;
        when "0101" =>
          if (wdptr = '0') then
            return "11100000";
          else
            return "00000111";
          end if;
        when "1000" =>
          if (wdptr = '0') then
            return "11110000";
          else
            return "00001111";
          end if;
        when "0111" =>
          if (wdptr = '0') then
            return "11111000";
          else
            return "00011111";
          end if;
        when "1001" =>
          if (wdptr = '0') then
            return "11111100";
          else
            return "00111111";
          end if;
        when "1010" =>
          if (wdptr = '0') then
            return "11111110";
          else
            return "01111111";
          end if;
        when others =>
          return "11111111";
      end case;
    end function;
 
    ---------------------------------------------------------------------------
    -- 
    ---------------------------------------------------------------------------
    variable seed1 : positive := 1;
    variable seed2: positive := 1;
 
    variable rdsize : std_logic_vector(3 downto 0);
    variable wdptr : std_logic;
    variable ioData : DoubleWordArray(0 to 31);
    variable frame : RioFrame;
 
  begin
    areset_n <= '0';
    enable <= '1';
 
    inboundWrite <= '0';
    outboundWrite <= '0';
    wbMessageWrite <= '0';
 
    writeFrameFull <= '0';
 
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    areset_n <= '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge");
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC1");
    PrintS("Description: Test maintenance requests.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC1-Step1");
    ---------------------------------------------------------------------------
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC2");
    PrintS("Description: Test request class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC2-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        rdsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNread(rdsize=>rdsize,
                                                      tid=>x"aa",
                                                      address=>"00000000000000000000000000000",
                                                      wdptr=>wdptr,
                                                      xamsbs=>"00")));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>getReadSize(rdsize, wdptr),
                                                          data=>ioData)));
 
        SetSlaveAccess(false, "0000000000000000000000000000000",
                       getReadMask(rdsize, wdptr),
                       getReadSize(rdsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    -- Test completed.
    ---------------------------------------------------------------------------
 
    TestEnd;
  end process;
 
  -----------------------------------------------------------------------------
  -- Instantiate the test object.
  -----------------------------------------------------------------------------
  TestObject: RioWbBridge
    generic map(
      EXTENDED_ADDRESS=>0,
      DEVICE_IDENTITY=>x"dead",
      DEVICE_VENDOR_IDENTITY=>x"beef",
      DEVICE_REV=>x"c0debabe",
      ASSY_IDENTITY=>x"1111",
      ASSY_VENDOR_IDENTITY=>x"2222",
      ASSY_REV=>x"3333")
    port map(
      clk=>clk,
      areset_n=>areset_n,
      enable=>enable,
      readFrameEmpty_i=>readFrameEmpty,
      readFrame_o=>readFrame,
      readContent_o=>readContent,
      readContentEnd_i=>readContentEnd,
      readContentData_i=>readContentData,
      writeFrameFull_i=>writeFrameFull,
      writeFrame_o=>writeFrame,
      writeFrameAbort_o=>writeFrameAbort,
      writeContent_o=>writeContent,
      writeContentData_o=>writeContentData,
      cyc_o=>wbCyc,
      stb_o=>wbStb,
      we_o=>wbWe,
      adr_o=>wbAdr,
      sel_o=>wbSel,
      dat_o=>wbDatWrite,
      dat_i=>wbDatRead,
      err_i=>wbErr,
      ack_i=>wbAck);
 
  -----------------------------------------------------------------------------
  -- Instantiate the test ports.
  -----------------------------------------------------------------------------
 
  TestPortPacketBufferInst: TestPortPacketBuffer
    port map(
      clk=>clk, areset_n=>areset_n,
      readEmpty_o=>inboundEmpty,
      readWrite_i=>inboundWrite,
      readMessage_i=>inboundMessage,
      readAck_o=>inboundAck,
      writeEmpty_o=>outboundEmpty,
      writeWrite_i=>outboundWrite,
      writeMessage_i=>outboundMessage,
      writeAck_o=>outboundAck,
      readFrameEmpty_o=>readFrameEmpty,
      readFrame_i=>readFrame,
      readFrameRestart_i=>'0',
      readFrameAborted_o=>readFrameAborted,
      readWindowEmpty_o=>open,
      readWindowReset_i=>'0',
      readWindowNext_i=>readFrame,
      readContentEmpty_o=>readContentEmpty,
      readContent_i=>readContent,
      readContentEnd_o=>readContentEnd,
      readContentData_o=>readContentData,
      writeFrame_i=>writeFrame,
      writeFrameAbort_i=>writeFrameAbort,
      writeContent_i=>writeContent,
      writeContentData_i=>writeContentData);
 
  TestPortWishboneInst: TestPortWishbone
    port map(
      clk=>clk,
      areset_n=>areset_n,
      messageEmpty_o=>wbMessageEmpty,
      messageWrite_i=>wbMessageWrite,
      message_i=>wbMessage,
      messageAck_o=>wbMessageAck,
      cyc_i=>wbCyc,
      stb_i=>wbStb,
      we_i=>wbWe,
      adr_i=>wbAdr,
      sel_i=>wbSel,
      dat_i=>wbDatWrite,
      dat_o=>wbDatRead,
      err_o=>wbErr,
      ack_o=>wbAck);
 
end architecture;

Line No.	Rev	Author	Line
1	42	magro732	`-------------------------------------------------------------------------------`
2			`--`
3			`-- RapidIO IP Library Core`
4			`--`
5			`-- This file is part of the RapidIO IP library project`
6			`-- http://www.opencores.org/cores/rio/`
7			`--`
8			`-- Description`
9			`-- Contains automatic test code to verify a RioWbBridge implementation.`
10			`--`
11			`-- To Do:`
12			`-- -`
13			`--`
14			`-- Author(s):`
15			`-- - Magnus Rosenius, magro732@opencores.org`
16			`--`
17			`-------------------------------------------------------------------------------`
18			`--`
19			`-- Copyright (C) 2013 Authors and OPENCORES.ORG`
20			`--`
21			`-- This source file may be used and distributed without`
22			`-- restriction provided that this copyright statement is not`
23			`-- removed from the file and that any derivative work contains`
24			`-- the original copyright notice and the associated disclaimer.`
25			`--`
26			`-- This source file is free software; you can redistribute it`
27			`-- and/or modify it under the terms of the GNU Lesser General`
28			`-- Public License as published by the Free Software Foundation;`
29			`-- either version 2.1 of the License, or (at your option) any`
30			`-- later version.`
31			`--`
32			`-- This source is distributed in the hope that it will be`
33			`-- useful, but WITHOUT ANY WARRANTY; without even the implied`
34			`-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
35			`-- PURPOSE. See the GNU Lesser General Public License for more`
36			`-- details.`
37			`--`
38			`-- You should have received a copy of the GNU Lesser General`
39			`-- Public License along with this source; if not, download it`
40			`-- from http://www.opencores.org/lgpl.shtml`
41			`--`
42			`-------------------------------------------------------------------------------`
43
44
45			`-- REMARK: Move the testport package and entities to a seperate file.`
46			`-------------------------------------------------------------------------------`
47			`--`
48			`-------------------------------------------------------------------------------`
49			`library ieee;`
50			`use ieee.std_logic_1164.all;`
51			`use work.rio_common.all;`
52
53			`-------------------------------------------------------------------------------`
54			`--`
55			`-------------------------------------------------------------------------------`
56			`package TestPortPackage is`
57			`constant ADDRESS_WIDTH : natural := 31;`
58			`constant DATA_SIZE_MAX : natural := 32;`
59
60			`type TestPortMessageWishbone is record`
61			`writeAccess : boolean;`
62			`address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
63			`byteSelect : std_logic_vector(7 downto 0);`
64			`length : natural range 1 to DATA_SIZE_MAX;`
65	44	magro732	`data : DoublewordArray(0 to DATA_SIZE_MAX-1);`
66	42	magro732	`latency : natural;`
67			`end record;`
68
69			`type TestPortMessageSymbol is record`
70			`symbolType : std_logic_vector(1 downto 0);`
71			`symbolContent : std_logic_vector(31 downto 0);`
72			`ignoreIdle : boolean;`
73			`end record;`
74
75			`type TestPortMessagePacketBuffer is record`
76			`frame : RioFrame;`
77			`willAbort : boolean;`
78			`end record;`
79
80			`-----------------------------------------------------------------------------`
81			`--`
82			`-----------------------------------------------------------------------------`
83
84			`component TestPortWishbone is`
85			`port(`
86			`clk : in std_logic;`
87			`areset_n : in std_logic;`
88
89			`messageEmpty_o : out std_logic;`
90			`messageWrite_i : in std_logic;`
91			`message_i : in TestPortMessageWishbone;`
92			`messageAck_o : out std_logic;`
93
94			`cyc_i : in std_logic;`
95			`stb_i : in std_logic;`
96			`we_i : in std_logic;`
97			`adr_i : in std_logic_vector(30 downto 0);`
98			`sel_i : in std_logic_vector(7 downto 0);`
99			`dat_i : in std_logic_vector(63 downto 0);`
100	44	magro732	`dat_o : out std_logic_vector(63 downto 0);`
101	42	magro732	`err_o : out std_logic;`
102			`ack_o : out std_logic);`
103			`end component;`
104
105			`component TestPortPacketBuffer is`
106			`port(`
107			`clk : in std_logic;`
108			`areset_n : in std_logic;`
109
110	44	magro732	`readEmpty_o : out std_logic;`
111			`readWrite_i : in std_logic;`
112			`readMessage_i : in TestPortMessagePacketBuffer;`
113			`readAck_o : out std_logic;`
114	42	magro732
115	44	magro732	`writeEmpty_o : out std_logic;`
116			`writeWrite_i : in std_logic;`
117			`writeMessage_i : in TestPortMessagePacketBuffer;`
118			`writeAck_o : out std_logic;`
119	42	magro732
120			`readFrameEmpty_o : out std_logic;`
121			`readFrame_i : in std_logic;`
122			`readFrameRestart_i : in std_logic;`
123			`readFrameAborted_o : out std_logic;`
124			`readWindowEmpty_o : out std_logic;`
125			`readWindowReset_i : in std_logic;`
126			`readWindowNext_i : in std_logic;`
127			`readContentEmpty_o : out std_logic;`
128			`readContent_i : in std_logic;`
129			`readContentEnd_o : out std_logic;`
130			`readContentData_o : out std_logic_vector(31 downto 0);`
131
132			`writeFrame_i : in std_logic;`
133			`writeFrameAbort_i : in std_logic;`
134			`writeContent_i : in std_logic;`
135			`writeContentData_i : in std_logic_vector(31 downto 0));`
136			`end component;`
137
138			`-----------------------------------------------------------------------------`
139			`--`
140			`-----------------------------------------------------------------------------`
141			`procedure TestPortWishboneWrite(`
142			`signal writeSignal : out std_logic;`
143			`signal messageSignal : out TestPortMessageWishbone;`
144			`signal ackSignal : in std_logic;`
145			`constant writeAccess : in boolean;`
146			`constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
147			`constant byteSelect : in std_logic_vector(7 downto 0);`
148			`constant length : in natural range 1 to DATA_SIZE_MAX;`
149			`constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);`
150			`constant latency : natural := 0);`
151
152			`procedure TestPortPacketBufferWrite(`
153			`signal writeSignal : out std_logic;`
154			`signal messageSignal : out TestPortMessagePacketBuffer;`
155			`signal ackSignal : in std_logic;`
156			`constant frame : in RioFrame;`
157			`constant willAbort : boolean := false);`
158
159			`end package;`
160
161			`-------------------------------------------------------------------------------`
162			`--`
163			`-------------------------------------------------------------------------------`
164			`package body TestPortPackage is`
165
166			`-----------------------------------------------------------------------------`
167			`--`
168			`-----------------------------------------------------------------------------`
169			`procedure TestPortWishboneWrite(`
170			`signal writeSignal : out std_logic;`
171			`signal messageSignal : out TestPortMessageWishbone;`
172			`signal ackSignal : in std_logic;`
173			`constant writeAccess : in boolean;`
174			`constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);`
175			`constant byteSelect : in std_logic_vector(7 downto 0);`
176			`constant length : in natural range 1 to DATA_SIZE_MAX;`
177			`constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);`
178			`constant latency : natural := 0) is`
179			`begin`
180			`writeSignal <= '1';`
181			`messageSignal.writeAccess <= writeAccess;`
182			`messageSignal.address <= address;`
183			`messageSignal.byteSelect <= byteSelect;`
184			`messageSignal.length <= length;`
185			`messageSignal.data <= data;`
186			`messageSignal.latency <= latency;`
187			`wait until ackSignal = '1';`
188			`writeSignal <= '0';`
189			`wait until ackSignal = '0';`
190			`end procedure;`
191
192			`-----------------------------------------------------------------------------`
193			`--`
194			`-----------------------------------------------------------------------------`
195			`procedure TestPortPacketBufferWrite(`
196			`signal writeSignal : out std_logic;`
197			`signal messageSignal : out TestPortMessagePacketBuffer;`
198			`signal ackSignal : in std_logic;`
199			`constant frame : in RioFrame;`
200			`constant willAbort : boolean := false) is`
201			`begin`
202			`writeSignal <= '1';`
203			`messageSignal.frame <= frame;`
204			`messageSignal.willAbort <= willAbort;`
205			`wait until ackSignal = '1';`
206			`writeSignal <= '0';`
207			`wait until ackSignal = '0';`
208			`end procedure;`
209
210			`end package body;`
211
212
213
214
215			`-------------------------------------------------------------------------------`
216			`--`
217			`-------------------------------------------------------------------------------`
218			`library ieee;`
219			`use ieee.std_logic_1164.all;`
220			`use ieee.numeric_std.all;`
221			`library std;`
222			`use std.textio.all;`
223			`use work.rio_common.all;`
224			`use work.TestPortPackage.all;`
225
226
227			`-------------------------------------------------------------------------------`
228			`--`
229			`-------------------------------------------------------------------------------`
230			`entity TestPortPacketBuffer is`
231			`port(`
232			`clk : in std_logic;`
233			`areset_n : in std_logic;`
234
235	44	magro732	`readEmpty_o : out std_logic;`
236			`readWrite_i : in std_logic;`
237			`readMessage_i : in TestPortMessagePacketBuffer;`
238			`readAck_o : out std_logic;`
239	42	magro732
240	44	magro732	`writeEmpty_o : out std_logic;`
241			`writeWrite_i : in std_logic;`
242			`writeMessage_i : in TestPortMessagePacketBuffer;`
243			`writeAck_o : out std_logic;`
244	42	magro732
245			`readFrameEmpty_o : out std_logic;`
246			`readFrame_i : in std_logic;`
247			`readFrameRestart_i : in std_logic;`
248			`readFrameAborted_o : out std_logic;`
249			`readWindowEmpty_o : out std_logic;`
250			`readWindowReset_i : in std_logic;`
251			`readWindowNext_i : in std_logic;`
252			`readContentEmpty_o : out std_logic;`
253			`readContent_i : in std_logic;`
254			`readContentEnd_o : out std_logic;`
255			`readContentData_o : out std_logic_vector(31 downto 0);`
256
257			`-- writeFrameFull_o is missing yes, but you can control it from the testbench directly`
258			`-- instead.`
259			`writeFrame_i : in std_logic;`
260			`writeFrameAbort_i : in std_logic;`
261			`writeContent_i : in std_logic;`
262			`writeContentData_i : in std_logic_vector(31 downto 0));`
263			`end entity;`
264
265
266			`-------------------------------------------------------------------------------`
267			`--`
268			`-------------------------------------------------------------------------------`
269			`architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is`
270			`constant QUEUE_SIZE : natural := 63;`
271	44	magro732	`type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;`
272	42	magro732
273			`function QueueIndexInc(constant i : natural) return natural is`
274			`variable returnValue : natural;`
275			`begin`
276			`if(i = QUEUE_SIZE) then`
277			`returnValue := 0;`
278			`else`
279			`returnValue := i + 1;`
280			`end if;`
281			`return returnValue;`
282			`end function;`
283
284			`begin`
285
286			`-----------------------------------------------------------------------------`
287			`--`
288			`-----------------------------------------------------------------------------`
289	44	magro732	`Reader: process`
290	42	magro732	`variable frameQueue : QueueArray(0 to QUEUE_SIZE);`
291			`variable front, back, window : natural range 0 to QUEUE_SIZE;`
292			`variable frameIndex : natural;`
293			`begin`
294			`wait until areset_n = '1';`
295
296			`readFrameEmpty_o <= '1';`
297			`readFrameAborted_o <= '0';`
298			`readWindowEmpty_o <= '1';`
299			`readContentEmpty_o <= '1';`
300			`readContentEnd_o <= '0';`
301			`readContentData_o <= (others=>'0');`
302
303			`front := 0;`
304			`back := 0;`
305			`window := 0;`
306			`frameIndex := 0;`
307	44	magro732	`readEmpty_o <= '1';`
308			`readAck_o <= '0';`
309	42	magro732
310			`loop`
311	44	magro732	`wait until clk = '1' or readWrite_i = '1';`
312	42	magro732
313			`if (clk'event) then`
314			`if (readFrame_i = '1') then`
315			`if (back /= front) then`
316			`back := QueueIndexInc(back);`
317			`else`
318	44	magro732	`TestError("READ:BACK:reading when no frame is present");`
319	42	magro732	`end if;`
320			`end if;`
321
322			`if (readFrameRestart_i = '1') then`
323			`frameIndex := 0;`
324			`end if;`
325
326			`if (readWindowReset_i = '1') then`
327			`window := back;`
328			`frameIndex := 0;`
329			`end if;`
330
331			`if (readWindowNext_i = '1') then`
332			`if (window /= front) then`
333			`window := QueueIndexInc(window);`
334			`frameIndex := 0;`
335			`else`
336	44	magro732	`TestError("READ:WINDOW:reading when no frame is present");`
337	42	magro732	`end if;`
338			`end if;`
339
340			`if (readContent_i = '1') then`
341			`if (back /= front) then`
342			`if (frameIndex < frameQueue(window).frame.length) then`
343			`readContentData_o <= frameQueue(window).frame.payload(frameIndex);`
344			`frameIndex := frameIndex + 1;`
345			`if (frameIndex = frameQueue(window).frame.length) then`
346			`readContentEnd_o <= '1';`
347			`else`
348			`readContentEnd_o <= '0';`
349			`end if;`
350			`else`
351	44	magro732	`TestError("READ:CONTENT:reading when frame has ended");`
352	42	magro732	`end if;`
353			`else`
354	44	magro732	`TestError("READ:CONTENT:reading when no frame is present");`
355	42	magro732	`end if;`
356			`end if;`
357
358			`if (front = back) then`
359			`readFrameEmpty_o <= '1';`
360			`else`
361			`readFrameEmpty_o <= '0';`
362			`end if;`
363
364			`if (front = window) then`
365			`readWindowEmpty_o <= '1';`
366			`readContentEmpty_o <= '1';`
367			`else`
368			`readWindowEmpty_o <= '0';`
369			`if (frameIndex /= frameQueue(window).frame.length) then`
370			`readContentEmpty_o <= '0';`
371			`else`
372			`readContentEmpty_o <= '1';`
373			`end if;`
374			`end if;`
375
376			`if (front = back) then`
377	44	magro732	`readEmpty_o <= '1';`
378	42	magro732	`else`
379	44	magro732	`readEmpty_o <= '0';`
380	42	magro732	`end if;`
381	44	magro732	`elsif (readWrite_i'event) then`
382			`frameQueue(front) := readMessage_i;`
383	42	magro732	`front := QueueIndexInc(front);`
384
385	44	magro732	`readEmpty_o <= '0';`
386			`readAck_o <= '1';`
387			`wait until readWrite_i = '0';`
388			`readAck_o <= '0';`
389	42	magro732	`end if;`
390			`end loop;`
391			`end process;`
392
393			`-----------------------------------------------------------------------------`
394			`--`
395			`-----------------------------------------------------------------------------`
396	44	magro732	`Writer: process`
397	42	magro732	`variable frameQueue : QueueArray(0 to QUEUE_SIZE);`
398			`variable front, back : natural range 0 to QUEUE_SIZE;`
399			`variable frameIndex : natural range 0 to 69;`
400			`begin`
401			`wait until areset_n = '1';`
402
403	44	magro732	`writeEmpty_o <= '1';`
404			`writeAck_o <= '0';`
405	42	magro732
406			`front := 0;`
407			`back := 0;`
408			`frameIndex := 0;`
409
410			`loop`
411	44	magro732	`wait until clk = '1' or writeWrite_i = '1';`
412	42	magro732
413			`if (clk'event) then`
414
415			`if (writeFrame_i = '1') then`
416			`if (frameIndex = 0) then`
417	44	magro732	`TestError("WRITE:Empty frame written.");`
418	42	magro732	`end if;`
419			`if (frameIndex /= frameQueue(back).frame.length) then`
420	44	magro732	`TestError("WRITE:Frame with unmatching length was written.");`
421	42	magro732	`end if;`
422			`if (back /= front) then`
423			`back := QueueIndexInc(back);`
424			`else`
425	44	magro732	`TestError("WRITE:Unexpected frame written.");`
426	42	magro732	`end if;`
427			`frameIndex := 0;`
428			`end if;`
429
430			`if (writeFrameAbort_i = '1') then`
431			`if (back /= front) then`
432			`if (frameQueue(back).willAbort) then`
433	44	magro732	`TestCompare(frameIndex,`
434			`frameQueue(back).frame.length,`
435			`"frameIndex abort");`
436	42	magro732	`back := QueueIndexInc(back);`
437			`else`
438	44	magro732	`TestError("WRITE:Not expecting this frame to abort.");`
439	42	magro732	`end if;`
440			`end if;`
441			`frameIndex := 0;`
442			`end if;`
443
444			`if (writeContent_i = '1') then`
445			`if (frameIndex < frameQueue(back).frame.length) then`
446	44	magro732	`TestCompare(writeContentData_i,`
447			`frameQueue(back).frame.payload(frameIndex),`
448			`"frame content");`
449	42	magro732	`frameIndex := frameIndex + 1;`
450			`else`
451	44	magro732	`TestError("WRITE:Receiving more frame content than expected.");`
452	42	magro732	`end if;`
453			`end if;`
454
455			`if (front = back) then`
456	44	magro732	`writeEmpty_o <= '1';`
457	42	magro732	`else`
458	44	magro732	`writeEmpty_o <= '0';`
459	42	magro732	`end if;`
460	44	magro732	`elsif (writeWrite_i'event) then`
461			`frameQueue(front) := writeMessage_i;`
462	42	magro732	`front := QueueIndexInc(front);`
463
464	44	magro732	`writeEmpty_o <= '0';`
465			`writeAck_o <= '1';`
466			`wait until writeWrite_i = '0';`
467			`writeAck_o <= '0';`
468	42	magro732	`end if;`
469			`end loop;`
470			`end process;`
471
472			`end architecture;`
473
474
475
476			`-------------------------------------------------------------------------------`
477			`--`
478			`-------------------------------------------------------------------------------`
479			`library ieee;`
480			`use ieee.std_logic_1164.all;`
481			`use ieee.numeric_std.all;`
482			`library std;`
483			`use std.textio.all;`
484			`use work.rio_common.all;`
485			`use work.TestPortPackage.all;`
486
487
488			`-------------------------------------------------------------------------------`
489			`--`
490			`-------------------------------------------------------------------------------`
491			`entity TestPortWishbone is`
492			`port(`
493			`clk : in std_logic;`
494			`areset_n : in std_logic;`
495
496			`messageEmpty_o : out std_logic;`
497			`messageWrite_i : in std_logic;`
498			`message_i : in TestPortMessageWishbone;`
499			`messageAck_o : out std_logic;`
500

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