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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains a platform to build endpoints on.
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--
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-- To Do:
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-- - Clean up the code for reading. Works but messy.
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--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- RioLogicalMaintenance
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-- This logical layer module handles ingress maintenance requests and converts
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-- them into accesses on a Wishbone similar bus accessing the configuration
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-- space.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rio_common.all;
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-------------------------------------------------------------------------------
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-- Entity for RioLogicalMaintenance.
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-------------------------------------------------------------------------------
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entity RioLogicalMaintenance is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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readRequestReady_i : in std_logic;
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writeRequestReady_i : in std_logic;
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size_i : in std_logic_vector(3 downto 0);
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offset_i : in std_logic_vector(20 downto 0);
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wdptr_i : in std_logic;
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payloadLength_i : in std_logic_vector(2 downto 0);
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payloadIndex_o : out std_logic_vector(2 downto 0);
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payload_i : in std_logic_vector(63 downto 0);
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done_o : out std_logic;
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readResponseReady_o : out std_logic;
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writeResponseReady_o : out std_logic;
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status_o : out std_logic_vector(3 downto 0);
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payloadLength_o : out std_logic_vector(2 downto 0);
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payloadIndex_i : in std_logic_vector(2 downto 0);
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payload_o : out std_logic_vector(63 downto 0);
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done_i : in std_logic;
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAdr_o : out std_logic_vector(21 downto 0);
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configDat_o : out std_logic_vector(31 downto 0);
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configDat_i : in std_logic_vector(31 downto 0);
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configAck_i : in std_logic);
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end entity;
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-------------------------------------------------------------------------------
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--
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-------------------------------------------------------------------------------
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architecture RioLogicalMaintenance of RioLogicalMaintenance is
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type StateType is (IDLE,
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CONFIG_READ_START, CONFIG_READ, CONFIG_READ_NEXT, CONFIG_READ_RESPONSE,
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CONFIG_WRITE_START, CONFIG_WRITE, CONFIG_WRITE_NEXT, CONFIG_WRITE_RESPONSE,
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WAIT_REQUEST);
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signal state : StateType;
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signal payloadLength : std_logic_vector(3 downto 0);
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signal payloadIndex : std_logic_vector(3 downto 0);
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signal payloadWrite : std_logic;
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signal payloadAddress : std_logic_vector(2 downto 0);
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signal payload : std_logic_vector(63 downto 0);
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signal configAdr : std_logic_vector(21 downto 0);
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signal configDat : std_logic_vector(31 downto 0);
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begin
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configAdr_o <= configAdr;
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configDat_o <= configDat;
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payloadLength_o <= payloadLength(3 downto 1);
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payloadIndex_o <= payloadIndex(3 downto 1);
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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Maintenance: process(clk, areset_n)
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begin
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if (areset_n = '0') then
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state <= IDLE;
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readResponseReady_o <= '0';
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writeResponseReady_o <= '0';
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done_o <= '0';
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configStb_o <= '0';
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configWe_o <= '0';
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configAdr <= (others=>'0');
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configDat <= (others=>'0');
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payloadWrite <= '0';
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payloadIndex <= (others=>'0');
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payload <= (others=>'0');
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elsif (clk'event and clk = '1') then
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payloadWrite <= '0';
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case state is
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when IDLE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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done_o <= '0';
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if (readRequestReady_i = '1') then
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state <= CONFIG_READ_START;
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elsif (writeRequestReady_i = '1') then
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state <= CONFIG_WRITE_START;
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end if;
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when CONFIG_READ_START =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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configStb_o <= '1';
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configWe_o <= '0';
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if (size_i = "1000") then
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configAdr <= offset_i & wdptr_i;
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else
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configAdr <= offset_i & '0';
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end if;
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payloadIndex <= "0000";
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payload <= (others=>'0');
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state <= CONFIG_READ;
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when CONFIG_READ =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (configAck_i = '1') then
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configStb_o <= '0';
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
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state <= CONFIG_READ_NEXT;
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end if;
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if (size_i = "1000") and (wdptr_i = '0') then
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payload(63 downto 32) <= configDat_i;
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elsif (size_i = "1000") and (wdptr_i = '1') then
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payload(31 downto 0) <= configDat_i;
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else
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if (payloadIndex(0) = '0') then
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payload(63 downto 32) <= configDat_i;
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else
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payload(31 downto 0) <= configDat_i;
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end if;
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end if;
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when CONFIG_READ_NEXT =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (size_i = "1000") and (wdptr_i = '0') then
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-- 1 word.
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status_o <= "0000";
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payloadLength <= "0010";
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payloadWrite <= '1';
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state <= CONFIG_READ_RESPONSE;
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elsif (size_i = "1000") and (wdptr_i = '1') then
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-- 1 word.
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status_o <= "0000";
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payloadLength <= "0010";
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payloadWrite <= '1';
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state <= CONFIG_READ_RESPONSE;
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elsif (size_i = "1011") and (wdptr_i = '0') then
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-- 2 words.
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status_o <= "0000";
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payloadLength <= "0010";
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payloadWrite <= payloadIndex(0);
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if (payloadIndex = "0001") then
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state <= CONFIG_READ_RESPONSE;
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else
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configStb_o <= '1';
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state <= CONFIG_READ;
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end if;
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elsif (size_i = "1011") and (wdptr_i = '1') then
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-- 4 words.
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status_o <= "0000";
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payloadLength <= "0100";
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payloadWrite <= payloadIndex(0);
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if (payloadIndex = "0011") then
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state <= CONFIG_READ_RESPONSE;
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else
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configStb_o <= '1';
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state <= CONFIG_READ;
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end if;
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elsif (size_i = "1100") and (wdptr_i = '0') then
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-- 8 words.
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status_o <= "0000";
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payloadLength <= "1000";
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payloadWrite <= payloadIndex(0);
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if (payloadIndex = "0111") then
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state <= CONFIG_READ_RESPONSE;
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else
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configStb_o <= '1';
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state <= CONFIG_READ;
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end if;
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elsif (size_i = "1100") and (wdptr_i = '1') then
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-- 16 words.
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status_o <= "0000";
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payloadLength <= "0000";
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payloadWrite <= payloadIndex(0);
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if (payloadIndex = "1111") then
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state <= CONFIG_READ_RESPONSE;
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else
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configStb_o <= '1';
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state <= CONFIG_READ;
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end if;
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else
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-- Unallowed packet.
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-- Send write-response with status indicating error.
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status_o <= "0111";
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state <= CONFIG_READ_RESPONSE;
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end if;
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payloadAddress <= payloadIndex(3 downto 1);
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payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
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when CONFIG_READ_RESPONSE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (done_i = '1') then
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readResponseReady_o <= '0';
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state <= WAIT_REQUEST;
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else
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readResponseReady_o <= '1';
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end if;
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when CONFIG_WRITE_START =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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configWe_o <= '1';
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if (size_i = "1000") then
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configAdr <= offset_i & wdptr_i;
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else
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configAdr <= offset_i & '0';
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283 |
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end if;
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284 |
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if (size_i = "1000") and (wdptr_i = '0') then
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-- 1 word.
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configStb_o <= '1';
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configDat <= payload_i(63 downto 32);
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payloadLength <= "0001";
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289 |
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status_o <= "0000";
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290 |
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state <= CONFIG_WRITE;
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291 |
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elsif (size_i = "1000") and (wdptr_i = '1') then
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-- 1 word.
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293 |
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configStb_o <= '1';
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294 |
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configDat <= payload_i(31 downto 0);
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295 |
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payloadLength <= "0001";
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296 |
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status_o <= "0000";
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297 |
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state <= CONFIG_WRITE;
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298 |
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elsif (size_i = "1011") and (wdptr_i = '0') then
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299 |
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-- 2 words.
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300 |
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configStb_o <= '1';
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301 |
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configDat <= payload_i(63 downto 32);
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302 |
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payloadLength <= "0010";
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303 |
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status_o <= "0000";
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304 |
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state <= CONFIG_WRITE;
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305 |
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elsif (size_i = "1011") and (wdptr_i = '1') then
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306 |
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-- maximum 4 words.
|
307 |
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configStb_o <= '1';
|
308 |
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configDat <= payload_i(63 downto 32);
|
309 |
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payloadLength <= payloadLength_i & '0';
|
310 |
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status_o <= "0000";
|
311 |
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state <= CONFIG_WRITE;
|
312 |
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elsif (size_i = "1100") and (wdptr_i = '0') then
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313 |
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-- maximum 8 words.
|
314 |
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configStb_o <= '1';
|
315 |
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configDat <= payload_i(63 downto 32);
|
316 |
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payloadLength <= payloadLength_i & '0';
|
317 |
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status_o <= "0000";
|
318 |
|
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state <= CONFIG_WRITE;
|
319 |
|
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elsif (size_i = "1100") and (wdptr_i = '1') then
|
320 |
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-- maximum 16 words.
|
321 |
|
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configStb_o <= '1';
|
322 |
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configDat <= payload_i(63 downto 32);
|
323 |
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payloadLength <= payloadLength_i & '0';
|
324 |
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status_o <= "0000";
|
325 |
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state <= CONFIG_WRITE;
|
326 |
|
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else
|
327 |
|
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-- Unallowed packet.
|
328 |
|
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-- Send write-response with status indicating error.
|
329 |
|
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status_o <= "0111";
|
330 |
|
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state <= CONFIG_WRITE_RESPONSE;
|
331 |
|
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end if;
|
332 |
|
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payloadIndex <= "0001";
|
333 |
|
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|
334 |
|
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when CONFIG_WRITE =>
|
335 |
|
|
---------------------------------------------------------------------
|
336 |
|
|
--
|
337 |
|
|
---------------------------------------------------------------------
|
338 |
|
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if (configAck_i = '1') then
|
339 |
|
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configStb_o <= '0';
|
340 |
|
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
|
341 |
|
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state <= CONFIG_WRITE_NEXT;
|
342 |
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end if;
|
343 |
|
|
|
344 |
|
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when CONFIG_WRITE_NEXT =>
|
345 |
|
|
---------------------------------------------------------------------
|
346 |
|
|
--
|
347 |
|
|
---------------------------------------------------------------------
|
348 |
|
|
if (payloadIndex(0) = '0') then
|
349 |
|
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configDat <= payload_i(63 downto 32);
|
350 |
|
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else
|
351 |
|
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configDat <= payload_i(31 downto 0);
|
352 |
|
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end if;
|
353 |
|
|
|
354 |
|
|
payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
|
355 |
|
|
if (payloadIndex /= payloadLength) then
|
356 |
|
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configStb_o <= '1';
|
357 |
|
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state <= CONFIG_WRITE;
|
358 |
|
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else
|
359 |
|
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state <= CONFIG_WRITE_RESPONSE;
|
360 |
|
|
end if;
|
361 |
|
|
|
362 |
|
|
when CONFIG_WRITE_RESPONSE =>
|
363 |
|
|
---------------------------------------------------------------------
|
364 |
|
|
--
|
365 |
|
|
---------------------------------------------------------------------
|
366 |
|
|
if (done_i = '1') then
|
367 |
|
|
writeResponseReady_o <= '0';
|
368 |
|
|
state <= WAIT_REQUEST;
|
369 |
|
|
else
|
370 |
|
|
writeResponseReady_o <= '1';
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
when WAIT_REQUEST =>
|
374 |
|
|
---------------------------------------------------------------------
|
375 |
|
|
--
|
376 |
|
|
---------------------------------------------------------------------
|
377 |
|
|
done_o <= '1';
|
378 |
|
|
if (readRequestReady_i = '0') and (writeRequestReady_i = '0') then
|
379 |
|
|
state <= IDLE;
|
380 |
|
|
end if;
|
381 |
|
|
when others =>
|
382 |
|
|
|
383 |
|
|
end case;
|
384 |
|
|
end if;
|
385 |
|
|
end process;
|
386 |
|
|
|
387 |
|
|
-----------------------------------------------------------------------------
|
388 |
|
|
-- Payload content memory.
|
389 |
|
|
-----------------------------------------------------------------------------
|
390 |
|
|
|
391 |
|
|
PayloadMemory: MemorySimpleDualPort
|
392 |
|
|
generic map(ADDRESS_WIDTH=>3, DATA_WIDTH=>64)
|
393 |
|
|
port map(clkA_i=>clk,
|
394 |
|
|
enableA_i=>payloadWrite,
|
395 |
|
|
addressA_i=>payloadAddress,
|
396 |
|
|
dataA_i=>payload,
|
397 |
|
|
clkB_i=>clk,
|
398 |
|
|
enableB_i=>'1',
|
399 |
|
|
addressB_i=>payloadIndex_i,
|
400 |
|
|
dataB_o=>payload_o);
|
401 |
|
|
|
402 |
|
|
end architecture;
|