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[/] [rio/] [branches/] [2.0.0-development/] [rtl/] [vhdl/] [RioWbBridge.vhd] - Blame information for rev 46

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1 6 magro732 
-------------------------------------------------------------------------------
2 
--
3 
-- RapidIO IP Library Core
4 
--
5 
-- This file is part of the RapidIO IP library project
6 
-- http://www.opencores.org/cores/rio/
7 
--
8 
-- Description
9 
-- Containing a bridge between a RapidIO network and a Wishbone bus. Packets
10 39 magro732 
-- NWRITE, NWRITER and NREAD are currently supported.
11 6 magro732 
--
12 
-- To Do:
13 46 magro732 
-- - Move packet handlers to RioLogicalPackets.
14 
-- - Move component declarations to riocommon.
15 
-- - Update the Maintenance handler to the new interface. It currently does not
16 
--   compile.
17 
-- - Set the stb_o to '0' in between read accesses to conform better to a
18 
--   block transfer in the Wishbone standard.
19 
-- - Clean up cyc-signals, only stb-signals are needed (between
20 
--   RioLogicalCommon and the packet handlers).
21 
-- - Add support for the lock_o to be sure to transfer all the packet
22 
--   content atomically?
23 
-- - Add support for EXTENDED_ADDRESS.
24 
-- - Add support for addressing to implementation defined config space by
25 
--   adding interface to top entity.
26 
-- - Use the baseDeviceId when sending packets? Currently, all responses
27 
--   are sent with destination<->source exchanged so the baseDeviceId is not
28 
--   needed.
29 
-- - Support inbound data with full bandwidth, not just half, applies to
30 
--   RioLogicalCommon and the packet handlers.
31 
-- - Move the packet handlers to seperate files.
32 
-- - Increase the priority of the response-packet when sent?
33 
-- - Implement error indications if erronous packets are received.
34 
-- - Implement error indications if err_i is received on the Wishbone bus.
35 
-- - Add support for extended features to dynamically configure the status
36 
--   from the port this block is connected to. Needed for the discovered- and
37 
--   masterEnable-bits.
38 
-- - Add support for outbound doorbells connected to interrupt input pins.
39 6 magro732 
--
40 
-- Author(s):
41 39 magro732 
-- - Magnus Rosenius, magro732@opencores.org
42 6 magro732 
--
43 
-------------------------------------------------------------------------------
44 
--
45 
-- Copyright (C) 2013 Authors and OPENCORES.ORG
46 
--
47 
-- This source file may be used and distributed without
48 
-- restriction provided that this copyright statement is not
49 
-- removed from the file and that any derivative work contains
50 
-- the original copyright notice and the associated disclaimer.
51 
--
52 
-- This source file is free software; you can redistribute it
53 
-- and/or modify it under the terms of the GNU Lesser General
54 
-- Public License as published by the Free Software Foundation;
55 
-- either version 2.1 of the License, or (at your option) any
56 
-- later version.
57 
--
58 
-- This source is distributed in the hope that it will be
59 
-- useful, but WITHOUT ANY WARRANTY; without even the implied
60 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
61 
-- PURPOSE. See the GNU Lesser General Public License for more
62 
-- details.
63 
--
64 
-- You should have received a copy of the GNU Lesser General
65 
-- Public License along with this source; if not, download it
66 
-- from http://www.opencores.org/lgpl.shtml
67 
--
68 
-------------------------------------------------------------------------------
69 
 
70 45 magro732 
 
71 39 magro732 
-------------------------------------------------------------------------------
72 
-- RioWbBridge.
73 45 magro732 
-- This block acts as an RapidIO endpoint and converts packets into Wishbone
74 
-- accesses.
75 39 magro732 
-------------------------------------------------------------------------------
76 6 magro732 
library ieee;
77 
use ieee.std_logic_1164.all;
78 42 magro732 
use ieee.numeric_std.all;
79 6 magro732 
use work.rio_common.all;
80 
 
81 
-------------------------------------------------------------------------------
82 39 magro732 
-- Entity for RioWbBridge.
83 6 magro732 
-------------------------------------------------------------------------------
84 39 magro732 
entity RioWbBridge is
85 6 magro732 
  generic(
86 39 magro732 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0;
87 6 magro732 
    DEVICE_IDENTITY : std_logic_vector(15 downto 0);
88 
    DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
89 
    DEVICE_REV : std_logic_vector(31 downto 0);
90 
    ASSY_IDENTITY : std_logic_vector(15 downto 0);
91 
    ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
92 39 magro732 
    ASSY_REV : std_logic_vector(15 downto 0));
93 6 magro732 
  port(
94 39 magro732 
    clk : in std_logic;
95 
    areset_n : in std_logic;
96 44 magro732 
    enable : in std_logic;
97 6 magro732 
 
98 
    readFrameEmpty_i : in std_logic;
99 
    readFrame_o : out std_logic;
100 
    readContent_o : out std_logic;
101 
    readContentEnd_i : in std_logic;
102 
    readContentData_i : in std_logic_vector(31 downto 0);
103 
    writeFrameFull_i : in std_logic;
104 
    writeFrame_o : out std_logic;
105 
    writeFrameAbort_o : out std_logic;
106 
    writeContent_o : out std_logic;
107 
    writeContentData_o : out std_logic_vector(31 downto 0);
108 
 
109 39 magro732 
    cyc_o : out std_logic;
110 
    stb_o : out std_logic;
111 
    we_o : out std_logic;
112 
    adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
113 
    sel_o : out std_logic_vector(7 downto 0);
114 
    dat_o : out std_logic_vector(63 downto 0);
115 
    dat_i : in std_logic_vector(63 downto 0);
116 
    err_i : in std_logic;
117 
    ack_i : in std_logic);
118 
end entity;
119 6 magro732 
 
120 39 magro732 
 
121 6 magro732 
-------------------------------------------------------------------------------
122 
-- Architecture for RioWbBridge.
123 
-------------------------------------------------------------------------------
124 39 magro732 
architecture RioWbBridgeImpl of RioWbBridge is
125 6 magro732 
 
126 39 magro732 
  component RequestClassInbound is
127 
    generic(
128 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
129 6 magro732 
    port(
130 39 magro732 
      clk : in std_logic;
131 
      areset_n : in std_logic;
132 
      enable : in std_logic;
133 
 
134 
      ready_o : out std_logic;
135 
      vc_o : out std_logic;
136 
      crf_o : out std_logic;
137 
      prio_o : out std_logic_vector(1 downto 0);
138 
      tt_o : out std_logic_vector(1 downto 0);
139 
      dstId_o : out std_logic_vector(31 downto 0);
140 
      srcId_o : out std_logic_vector(31 downto 0);
141 
      tid_o : out std_logic_vector(7 downto 0);
142 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
143 44 magro732 
      length_o : out std_logic_vector(4 downto 0);
144 39 magro732 
      select_o : out std_logic_vector(7 downto 0);
145 
      done_i : in std_logic;
146 
 
147 45 magro732 
      inboundCyc_i : in std_logic;
148 
      inboundStb_i : in std_logic;
149 
      inboundAdr_i : in std_logic_vector(7 downto 0);
150 
      inboundDat_i : in std_logic_vector(31 downto 0);
151 
      inboundAck_o : out std_logic);
152 6 magro732 
  end component;
153 
 
154 39 magro732 
  component WriteClassInbound is
155 
    generic(
156 
      EXTENDED_ADDRESS : natural range 0 to 2 := 0);
157 
    port(
158 
      clk : in std_logic;
159 
      areset_n : in std_logic;
160 
      enable : in std_logic;
161 6 magro732 
 
162 39 magro732 
      ready_o : out std_logic;
163 45 magro732 
      responseNeeded_o : out std_logic;
164 39 magro732 
      vc_o : out std_logic;
165 
      crf_o : out std_logic;
166 
      prio_o : out std_logic_vector(1 downto 0);
167 
      tt_o : out std_logic_vector(1 downto 0);
168 
      dstId_o : out std_logic_vector(31 downto 0);
169 
      srcId_o : out std_logic_vector(31 downto 0);
170 
      tid_o : out std_logic_vector(7 downto 0);
171 
      address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
172 44 magro732 
      length_o : out std_logic_vector(4 downto 0);
173 39 magro732 
      select_o : out std_logic_vector(7 downto 0);
174 44 magro732 
      payloadRead_i : in std_logic;
175 
      payloadIndex_i : in std_logic_vector(4 downto 0);
176 
      payload_o : out std_logic_vector(63 downto 0);
177 39 magro732 
      done_i : in std_logic;
178 
 
179 45 magro732 
      inboundCyc_i : in std_logic;
180 
      inboundStb_i : in std_logic;
181 
      inboundAdr_i : in std_logic_vector(7 downto 0);
182 
      inboundDat_i : in std_logic_vector(31 downto 0);
183 
      inboundAck_o : out std_logic);
184 39 magro732 
  end component;
185 6 magro732 
 
186 39 magro732 
  component ResponseClassOutbound is
187 
    port(
188 
      clk : in std_logic;
189 
      areset_n : in std_logic;
190 
      enable : in std_logic;
191 6 magro732 
 
192 39 magro732 
      ready_i : in std_logic;
193 
      vc_i : in std_logic;
194 
      crf_i : in std_logic;
195 
      prio_i : in std_logic_vector(1 downto 0);
196 
      tt_i : in std_logic_vector(1 downto 0);
197 
      dstid_i : in std_logic_vector(31 downto 0);
198 
      srcid_i : in std_logic_vector(31 downto 0);
199 
      tid_i : in std_logic_vector(7 downto 0);
200 
      error_i : in std_logic;
201 
      payloadPresent_i :  in std_logic;
202 44 magro732 
      payloadLength_i : in std_logic_vector(4 downto 0);
203 39 magro732 
      payloadWrite_i : in std_logic;
204 44 magro732 
      payloadIndex_i : in std_logic_vector(4 downto 0);
205 
      payload_i : in std_logic_vector(63 downto 0);
206 39 magro732 
      done_o : out std_logic;
207 
 
208 45 magro732 
      outboundCyc_o : out std_logic;
209 
      outboundStb_o : out std_logic;
210 
      outboundDat_o : out std_logic_vector(31 downto 0);
211 
      outboundAck_i : in std_logic);
212 39 magro732 
  end component;
213 6 magro732 
 
214 45 magro732 
  constant PORTS : natural := 2;
215 
 
216 44 magro732 
  type StateType is (IDLE,
217 
                     REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
218 45 magro732 
                     WRITE_CLASS, WRITE_CLASS_ACCESS, WRITE_CLASS_ACK, WRITE_CLASS_RESPONSE);
219 44 magro732 
  signal state : StateType;
220 
 
221 
  signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
222 
  signal datOut : std_logic_vector(63 downto 0);
223 
 
224 
  signal payloadUpdate : std_logic;
225 
  signal payloadIndex : std_logic_vector(4 downto 0);
226 
 
227 
  signal requestReady : std_logic;
228 
  signal requestVc : std_logic;
229 
  signal requestCrf : std_logic;
230 
  signal requestPrio : std_logic_vector(1 downto 0);
231 
  signal requestTt : std_logic_vector(1 downto 0);
232 
  signal requestDstId : std_logic_vector(31 downto 0);
233 
  signal requestSrcId : std_logic_vector(31 downto 0);
234 
  signal requestTid : std_logic_vector(7 downto 0);
235 
  signal requestAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
236 
  signal requestLength : std_logic_vector(4 downto 0);
237 
  signal requestSelect : std_logic_vector(7 downto 0);
238 
  signal requestDone : std_logic;
239 
  signal requestAck : std_logic;
240 
 
241 
  signal writeReady : std_logic;
242 45 magro732 
  signal writeResponse : std_logic;
243 44 magro732 
  signal writeVc : std_logic;
244 
  signal writeCrf : std_logic;
245 
  signal writePrio : std_logic_vector(1 downto 0);
246 
  signal writeTt : std_logic_vector(1 downto 0);
247 
  signal writeDstId : std_logic_vector(31 downto 0);
248 
  signal writeSrcId : std_logic_vector(31 downto 0);
249 
  signal writeTid : std_logic_vector(7 downto 0);
250 
  signal writeAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
251 
  signal writeLength : std_logic_vector(4 downto 0);
252 
  signal writeSelect : std_logic_vector(7 downto 0);
253 
  signal writePayload : std_logic_vector(63 downto 0);
254 
  signal writeDone : std_logic;
255 
  signal writeAck : std_logic;
256 
 
257 
  signal responseReady : std_logic;
258 
  signal responseVc : std_logic;
259 
  signal responseCrf : std_logic;
260 
  signal responsePrio : std_logic_vector(1 downto 0);
261 
  signal responseTt : std_logic_vector(1 downto 0);
262 
  signal responseDstId : std_logic_vector(31 downto 0);
263 
  signal responseSrcId : std_logic_vector(31 downto 0);
264 
  signal responseTid : std_logic_vector(7 downto 0);
265 
  signal responseError : std_logic;
266 
  signal responsePayloadPresent : std_logic;
267 
  signal responsePayload : std_logic_vector(63 downto 0);
268 
  signal responseDone : std_logic;
269 
 
270 46 magro732 
  signal readRequestInbound : std_logic;
271 
  signal writeRequestInbound : std_logic;
272 
  signal vcInbound : std_logic;
273 
  signal crfInbound : std_logic;
274 
  signal prioInbound : std_logic_vector(1 downto 0);
275 
  signal ttInbound : std_logic_vector(1 downto 0);
276 
  signal dstIdInbound : std_logic_vector(31 downto 0);
277 
  signal srcIdInbound : std_logic_vector(31 downto 0);
278 
  signal tidInbound : std_logic_vector(7 downto 0);
279 
  signal offsetInbound : std_logic_vector(20 downto 0);
280 
  signal wdptrInbound : std_logic;
281 
  signal payloadLengthInbound : std_logic_vector(3 downto 0);
282 
  signal payloadInbound : std_logic_vector(31 downto 0);
283 
 
284 
  signal readResponseMaint : std_logic;
285 
  signal writeResponseMaint : std_logic;
286 
  signal wdptrMaint : std_logic;
287 
  signal payloadLengthMaint : std_logic_vector(3 downto 0);
288 
  signal payloadIndexMaint : std_logic_vector(3 downto 0);
289 
  signal payloadMaint : std_logic_vector(31 downto 0);
290 
  signal doneMaint : std_logic;
291 
 
292 
  signal payloadIndexOutbound : std_logic_vector(3 downto 0);
293 
  signal doneOutbound : std_logic;
294 
 
295 45 magro732 
  signal configStb : std_logic;
296 
  signal configWe : std_logic;
297 
  signal configAdr : std_logic_vector(21 downto 0);
298 
  signal configAdrByte : std_logic_vector(23 downto 0);
299 
  signal configDatWrite : std_logic_vector(31 downto 0);
300 
  signal configDatRead : std_logic_vector(31 downto 0);
301 
  signal configAck : std_logic;
302 
  signal maintenanceAck : std_logic;
303 
 
304 44 magro732 
  signal inboundCyc : std_logic;
305 
  signal inboundStb : std_logic;
306 
  signal inboundAdr : std_logic_vector(7 downto 0);
307 
  signal inboundDat : std_logic_vector(31 downto 0);
308 
  signal inboundAck : std_logic;
309 
 
310 45 magro732 
  signal outboundCyc : std_logic_vector(PORTS-1 downto 0);
311 
  signal outboundStb : std_logic_vector(PORTS-1 downto 0);
312 
  signal outboundDat : std_logic_vector(32*PORTS-1 downto 0);
313 
  signal outboundAck : std_logic_vector(PORTS-1 downto 0);
314 39 magro732 
 
315 
begin
316 
 
317 44 magro732 
  responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
318 
  responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
319 
  responsePrio <= requestPrio when (responsePayloadPresent = '1') else writePrio;
320 
  responseTt <= requestTt when (responsePayloadPresent = '1') else writeTt;
321 
  responseDstId <= requestSrcId when (responsePayloadPresent = '1') else writeSrcId;
322 
  responseSrcId <= requestDstId when (responsePayloadPresent = '1') else writeDstId;
323 
  responseTid <= requestTid when (responsePayloadPresent = '1') else writeTid;
324 
 
325 6 magro732 
  -----------------------------------------------------------------------------
326 39 magro732 
  --
327 6 magro732 
  -----------------------------------------------------------------------------
328 39 magro732 
  adr_o <= adr;
329 
  dat_o <= datOut;
330 
 
331 
  Bridge: process(clk, areset_n)
332 6 magro732 
  begin
333 39 magro732 
    if (areset_n = '0') then
334 
      cyc_o <= '0';
335 
      stb_o <= '0';
336 
      we_o <= '0';
337 
      adr <= (others=>'0');
338 
      datOut <= (others=>'0');
339 6 magro732 
 
340 44 magro732 
      payloadUpdate <= '0';
341 
      payloadIndex <= (others=>'0');
342 
 
343 39 magro732 
      requestDone <= '0';
344 
 
345 44 magro732 
      writeDone <= '0';
346 
 
347 
      responseReady <= '0';
348 
      responseError <= '0';
349 
      responsePayloadPresent <= '0';
350 
      responsePayload <= (others=>'0');
351 39 magro732 
    elsif (clk'event and clk = '1') then
352 44 magro732 
      if (enable = '1') then
353 
        requestDone <= '0';
354 
        writeDone <= '0';
355 
        responseReady <= '0';
356 
 
357 
        payloadUpdate <= '0';
358 
        if (payloadUpdate = '1') then
359 
          payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
360 
        end if;
361 
 
362 
        case state is
363 
          when IDLE =>
364 
            ---------------------------------------------------------------------
365 
            --
366 
            ---------------------------------------------------------------------
367 
            if (requestReady = '1') then
368 
              cyc_o <= '1';
369 
              stb_o <= '1';
370 
              we_o <= '0';
371 
              adr <= requestAddress;
372 
              sel_o <= requestSelect;
373 
 
374 
              payloadIndex <= (others=>'0');
375 
 
376 
              responsePayloadPresent <= '1';
377 
              state <= REQUEST_CLASS;
378 
            elsif (writeReady = '1') then
379 
              adr <= writeAddress;
380 39 magro732 
 
381 44 magro732 
              payloadUpdate <= '1';
382 
              payloadIndex <= (others=>'0');
383 
 
384 
              responsePayloadPresent <= '0';
385 
              state <= WRITE_CLASS;
386 
            end if;
387 39 magro732 
 
388 44 magro732 
          when REQUEST_CLASS =>
389 
            ---------------------------------------------------------------------
390 
            --
391 
            ---------------------------------------------------------------------
392 
            if (ack_i = '1') then
393 
              -- Note that responsePayloadIndex is updated after the write has been made.
394 
              payloadUpdate <= '1';
395 
              responsePayload <= dat_i;
396 
 
397 39 magro732 
              adr <= std_logic_vector(unsigned(adr) + 1);
398 44 magro732 
 
399 
              if (payloadIndex = requestLength) then
400 
                requestDone <= '1';
401 
                cyc_o <= '0';
402 
                stb_o <= '0';
403 
                state <= REQUEST_CLASS_RESPONSE;
404 
              end if;
405 39 magro732 
--          elsif(err_i = '1') then
406 
--            REMARK: Implement error indication from wb-bus...
407 44 magro732 
            end if;
408 39 magro732 
 
409 44 magro732 
          when REQUEST_CLASS_RESPONSE =>
410 
            ---------------------------------------------------------------------
411 
            --
412 
            ---------------------------------------------------------------------
413 
            if (responseDone = '1') then
414 
              responseReady <= '0';
415 
              state <= IDLE;
416 
            else
417 
              responseReady <= '1';
418 
            end if;
419 6 magro732 
 
420 44 magro732 
          when WRITE_CLASS =>
421 
            ---------------------------------------------------------------------
422 
            --
423 
            ---------------------------------------------------------------------
424 45 magro732 
            state <= WRITE_CLASS_ACCESS;
425 
 
426 
          when WRITE_CLASS_ACCESS =>
427 
            ---------------------------------------------------------------------
428 
            --
429 
            ---------------------------------------------------------------------
430 
            cyc_o <= '1';
431 
            stb_o <= '1';
432 
            we_o <= '1';
433 
            sel_o <= writeSelect;
434 
            datOut <= writePayload;
435 
            payloadUpdate <= '1';
436 
 
437 
            state <= WRITE_CLASS_ACK;
438 
 
439 
          when WRITE_CLASS_ACK =>
440 
            ---------------------------------------------------------------------
441 
            --
442 
            ---------------------------------------------------------------------
443 44 magro732 
            if (ack_i = '1') then
444 
              adr <= std_logic_vector(unsigned(adr) + 1);
445 
 
446 45 magro732 
              if (unsigned(payloadIndex) /= (unsigned(writeLength)+2)) then
447 
                stb_o <= '0';
448 
                state <= WRITE_CLASS_ACCESS;
449 44 magro732 
              else
450 
                writeDone <= '1';
451 
                cyc_o <= '0';
452 
                stb_o <= '0';
453 
                state <= WRITE_CLASS_RESPONSE;
454 
              end if;
455 
            end if;
456 
 
457 
          when WRITE_CLASS_RESPONSE =>
458 
            ---------------------------------------------------------------------
459 
            --
460 
            ---------------------------------------------------------------------
461 45 magro732 
            if (responseDone = '1') or (writeResponse = '0') then
462 44 magro732 
              responseReady <= '0';
463 
              state <= IDLE;
464 39 magro732 
            else
465 44 magro732 
              responseReady <= '1';
466 39 magro732 
            end if;
467 6 magro732 
 
468 44 magro732 
          when others =>
469 6 magro732 
 
470 44 magro732 
        end case;
471 
      end if;
472 39 magro732 
    end if;
473 
  end process;
474 
 
475 
  -----------------------------------------------------------------------------
476 45 magro732 
  -- Packet handlers.
477 39 magro732 
  -----------------------------------------------------------------------------
478 6 magro732 
 
479 39 magro732 
  RequestClassInboundInst: RequestClassInbound
480 
    generic map(
481 
      EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
482 
    port map(
483 
      clk=>clk,
484 
      areset_n=>areset_n,
485 
      enable=>enable,
486 
      ready_o=>requestReady,
487 
      vc_o=>requestVc,
488 
      crf_o=>requestCrf,
489 
      prio_o=>requestPrio,
490 
      tt_o=>requestTt,
491 
      dstId_o=>requestDstId,
492 
      srcId_o=>requestSrcId,
493 
      tid_o=>requestTid,
494 
      address_o=>requestAddress,
495 44 magro732 
      length_o=>requestLength,
496 39 magro732 
      select_o=>requestSelect,
497 
      done_i=>requestDone,
498 45 magro732 
      inboundCyc_i=>inboundCyc,
499 
      inboundStb_i=>inboundStb,
500 
      inboundAdr_i=>inboundAdr,
501 
      inboundDat_i=>inboundDat,
502 
      inboundAck_o=>requestAck);
503 6 magro732 
 
504 39 magro732 
  WriteClassInboundInst: WriteClassInbound
505 
    generic map(
506 
      EXTENDED_ADDRESS=>EXTENDED_ADDRESS)
507 
    port map(
508 
      clk=>clk,
509 
      areset_n=>areset_n,
510 
      enable=>enable,
511 
      ready_o=>writeReady,
512 45 magro732 
      responseNeeded_o=>writeResponse,
513 39 magro732 
      vc_o=>writeVc,
514 
      crf_o=>writeCrf,
515 
      prio_o=>writePrio,
516 
      tt_o=>writeTt,
517 
      dstId_o=>writeDstId,
518 
      srcId_o=>writeSrcId,
519 
      tid_o=>writeTid,
520 
      address_o=>writeAddress,
521 
      length_o=>writeLength,
522 
      select_o=>writeSelect,
523 44 magro732 
      payloadRead_i=>payloadUpdate,
524 
      payloadIndex_i=>payloadIndex,
525 39 magro732 
      payload_o=>writePayload,
526 
      done_i=>writeDone,
527 45 magro732 
      inboundCyc_i=>inboundCyc,
528 
      inboundStb_i=>inboundStb,
529 
      inboundAdr_i=>inboundAdr,
530 
      inboundDat_i=>inboundDat,
531 
      inboundAck_o=>writeAck);
532 6 magro732 
 
533 39 magro732 
  ResponseClassOutboundInst: ResponseClassOutbound
534 
    port map(
535 
      clk=>clk,
536 
      areset_n=>areset_n,
537 
      enable=>enable,
538 
      ready_i=>responseReady,
539 44 magro732 
      vc_i=>responseVc,
540 
      crf_i=>responseCrf,
541 
      prio_i=>responsePrio,
542 
      tt_i=>responseTt,
543 
      dstid_i=>responseDstId,
544 
      srcid_i=>responseSrcId,
545 
      tid_i=>responseTid,
546 39 magro732 
      error_i=>responseError,
547 
      payloadPresent_i=>responsePayloadPresent,
548 44 magro732 
      payloadLength_i=>requestLength,
549 
      payloadWrite_i=>payloadUpdate,
550 
      payloadIndex_i=>payloadIndex,
551 39 magro732 
      payload_i=>responsePayload,
552 
      done_o=>responseDone,
553 45 magro732 
      outboundCyc_o=>outboundCyc(0),
554 
      outboundStb_o=>outboundStb(0),
555 
      outboundDat_o=>outboundDat(31 downto 0),
556 
      outboundAck_i=>outboundAck(0));
557 44 magro732 
 
558 46 magro732 
  -----------------------------------------------------------------------------
559 45 magro732 
  -- Maintenance packet processing.
560 46 magro732 
  -----------------------------------------------------------------------------
561 
  InboundMaintenance: MaintenanceInbound
562 45 magro732 
    port map(
563 46 magro732 
      clk=>clk, areset_n=>areset_n, enable=>enable,
564 
      readRequestReady_o=>readRequestInbound,
565 
      writeRequestReady_o=>writeRequestInbound,
566 
      readResponseReady_o=>open,
567 
      writeResponseReady_o=>open,
568 
      portWriteReady_o=>open,
569 
      vc_o=>vcInbound,
570 
      crf_o=>crfInbound,
571 
      prio_o=>prioInbound,
572 
      tt_o=>ttInbound,
573 
      dstid_o=>dstIdInbound,
574 
      srcid_o=>srcIdInbound,
575 
      tid_o=>tidInbound,
576 
      hop_o=>open,
577 
      offset_o=>offsetInbound,
578 
      wdptr_o=>wdptrInbound,
579 
      payloadLength_o=>payloadLengthInbound,
580 
      payloadIndex_i=>payloadIndexMaint,
581 
      payload_o=>payloadInbound,
582 
      done_i=>doneMaint,
583 
      inboundCyc_i=>inboundCyc,
584 
      inboundStb_i=>inboundStb,
585 
      inboundAdr_i=>inboundAdr,
586 
      inboundDat_i=>inboundDat,
587 
      inboundAck_o=>maintenanceAck);
588 
 
589 
  OutboundMaintenance: MaintenanceOutbound
590 
    port map(
591 
      clk=>clk, areset_n=>areset_n, enable=>enable,
592 
      readRequestReady_i=>'0',
593 
      writeRequestReady_i=>'0',
594 
      readResponseReady_i=>readResponseMaint,
595 
      writeResponseReady_i=>writeResponseMaint,
596 
      portWriteReady_i=>'0',
597 
      vc_i=>vcInbound,
598 
      crf_i=>crfInbound,
599 
      prio_i=>prioInbound,
600 
      tt_i=>ttInbound,
601 
      dstid_i=>srcIdInbound,
602 
      srcid_i=>dstIdInbound,
603 
      status_i=>"0000",
604 
      tid_i=>tidInbound,
605 
      hop_i=>x"ff",
606 
      offset_i=>(others=>'0'),
607 
      wdptr_i=>wdptrMaint,
608 
      payloadLength_i=>payloadLengthMaint,
609 
      payloadIndex_o=>payloadIndexOutbound,
610 
      payload_i=>payloadMaint,
611 
      done_o=>doneOutbound,
612 
      outboundCyc_o=>outboundCyc(1),
613 
      outboundStb_o=>outboundStb(1),
614 
      outboundDat_o=>outboundDat(63 downto 32),
615 45 magro732 
      outboundAck_i=>outboundAck(1));
616 
 
617 46 magro732 
  MaintenanceBridge: RioLogicalMaintenance
618 
    port map(
619 
      clk=>clk, areset_n=>areset_n, enable=>enable,
620 
      readRequestReady_i=>readRequestInbound,
621 
      writeRequestReady_i=>writeRequestInbound,
622 
      offset_i=>offsetInbound,
623 
      wdptr_i=>wdptrInbound,
624 
      payloadLength_i=>payloadLengthInbound,
625 
      payloadIndex_o=>payloadIndexMaint,
626 
      payload_i=>payloadInbound,
627 
      done_o=>doneMaint,
628 
      readResponseReady_o=>readResponseMaint,
629 
      writeResponseReady_o=>writeResponseMaint,
630 
      wdptr_o=>wdptrMaint,
631 
      payloadLength_o=>payloadLengthMaint,
632 
      payloadIndex_i=>payloadIndexOutbound,
633 
      payload_o=>payloadMaint,
634 
      done_i=>doneOutbound,
635 
      configStb_o=>configStb,
636 
      configWe_o=>configWe,
637 
      configAdr_o=>configAdr,
638 
      configDat_o=>configDatWrite,
639 
      configDat_i=>configDatRead,
640 
      configAck_i=>configAck);
641 
 
642 45 magro732 
  -----------------------------------------------------------------------------
643 
  -- Common interface toward the packet queues.
644 
  -----------------------------------------------------------------------------
645 
 
646 
  inboundAck <= requestAck or writeAck or maintenanceAck;
647 39 magro732 
  RioLogicalCommonInst: RioLogicalCommon
648 45 magro732 
    generic map(PORTS=>PORTS)
649 39 magro732 
    port map(
650 
      clk=>clk,
651 
      areset_n=>areset_n,
652 
      enable=>enable,
653 
      readFrameEmpty_i=>readFrameEmpty_i,
654 
      readFrame_o=>readFrame_o,
655 
      readContent_o=>readContent_o,
656 
      readContentEnd_i=>readContentEnd_i,
657 
      readContentData_i=>readContentData_i,
658 
      writeFrameFull_i=>writeFrameFull_i,
659 
      writeFrame_o=>writeFrame_o,
660 
      writeFrameAbort_o=>writeFrameAbort_o,
661 
      writeContent_o=>writeContent_o,
662 
      writeContentData_o=>writeContentData_o,
663 45 magro732 
      inboundCyc_o=>inboundCyc,
664 
      inboundStb_o=>inboundStb,
665 
      inboundAdr_o=>inboundAdr,
666 
      inboundDat_o=>inboundDat,
667 
      inboundAck_i=>inboundAck,
668 
      outboundCyc_i=>outboundCyc,
669 
      outboundStb_i=>outboundStb,
670 
      outboundDat_i=>outboundDat,
671 
      outboundAck_o=>outboundAck);
672 6 magro732 
 
673 39 magro732 
  -----------------------------------------------------------------------------
674 
  -- Configuration memory.
675 
  -----------------------------------------------------------------------------
676 45 magro732 
  configAdrByte <= configAdr & "00";
677 
  memoryConfig : process(clk, areset_n)
678 
    variable componentTag : std_logic_vector(31 downto 0);
679 
    variable hostBaseDeviceIdLocked : std_logic;
680 
    variable hostBaseDeviceId : std_logic_vector(15 downto 0);
681 
  begin
682 
    if (areset_n = '0') then
683 
      componentTag := (others => '0');
684 
      hostBaseDeviceIdLocked := '0';
685 
      hostBaseDeviceId := (others => '1');
686 6 magro732 
 
687 45 magro732 
      configDatRead <= (others => '0');
688 
      configAck <= '0';
689 
    elsif (clk'event and clk = '1') then
690 
      if (configAck = '0') then
691 
        if (configStb = '1') then
692 
          configAck <= '1';
693 
          configDatRead <= (others=>'0');
694 
 
695 
          -- Check the address the access is for.
696 
          case (configAdrByte) is
697 
            when x"000000" =>
698 
              -----------------------------------------------------------------
699 
              -- Device Identity CAR. Read-only.
700 
              -----------------------------------------------------------------
701 
              configDatRead(31 downto 16) <= DEVICE_IDENTITY;
702 
              configDatRead(15 downto 0) <= DEVICE_VENDOR_IDENTITY;
703 
 
704 
            when x"000004" =>
705 
              -----------------------------------------------------------------
706 
              -- Device Information CAR. Read-only.
707 
              -----------------------------------------------------------------
708 
              configDatRead(31 downto 0) <= DEVICE_REV;
709 
 
710 
            when x"000008" =>
711 
              -----------------------------------------------------------------
712 
              -- Assembly Identity CAR. Read-only.
713 
              -----------------------------------------------------------------
714 
              configDatRead(31 downto 16) <= ASSY_IDENTITY;
715 
              configDatRead(15 downto 0) <= ASSY_VENDOR_IDENTITY;
716 
 
717 
            when x"00000c" =>
718 
              -----------------------------------------------------------------
719 
              -- Assembly Information CAR. Read-only.
720 
              -----------------------------------------------------------------
721 
              configDatRead(31 downto 16) <= ASSY_REV;
722 
 
723 
            when x"000010" =>
724 
              -----------------------------------------------------------------
725 
              -- Processing Element Features CAR. Read-only.
726 
              -----------------------------------------------------------------
727 
              -- Bridge.
728 
              configDatRead(31) <= '1';
729 
              -- Extended addressing support, 34-bit addresses.
730 
              configDatRead(2 downto 0) <= "001";
731 
 
732 
            when x"000018" =>
733 
              -----------------------------------------------------------------
734 
              -- Source Operations CAR. Read-only.
735 
              -----------------------------------------------------------------
736 
              -- Cannot act as a source of any packets.
737 
 
738 
            when x"00001c" =>
739 
              -----------------------------------------------------------------
740 
              -- Destination Operations CAR. Read-only.
741 
              -----------------------------------------------------------------
742 
              -- Read, supported.
743 
              configDatRead(15) <= '1';
744 
              -- Write, supported.
745 
              configDatRead(14) <= '1';
746 
              -- Write-with-response, supported.
747 
              configDatRead(12) <= '1';
748 
 
749 
            when x"00004c" =>
750 
              -----------------------------------------------------------------
751 
              -- Processing Element Logical Layer Control CSR.
752 
              -----------------------------------------------------------------
753 
              -- Extended addressing control, PE supports 34 bits addresses.
754 
              configDatRead(2 downto 0) <= "001";
755 6 magro732 
 
756 45 magro732 
            when x"000060" =>
757 
              -----------------------------------------------------------------
758 
              -- Base Device ID CSR.
759 
              -----------------------------------------------------------------
760 
              -- This is not used since this endpoint only replies to packets
761 
              -- and it can then use the destination deviceId as a source.
762 
 
763 
            when x"000068" =>
764 
              -----------------------------------------------------------------
765 
              -- Host Base Device ID Lock CSR.
766 
              -----------------------------------------------------------------
767 6 magro732 
 
768 45 magro732 
              -- Check if writing.
769 
              if (configWe = '1') then
770 
                -- Write access.
771 
 
772 
                -- Check if this field has been written before.
773 
                if (hostBaseDeviceIdLocked = '0') then
774 
                  -- The field has not been written.
775 
                  -- Lock the field and set the host base device id.
776 
                  hostBaseDeviceIdLocked := '1';
777 
                  hostBaseDeviceId := configDatWrite(15 downto 0);
778 
                else
779 
                  -- The field has been written.
780 
                  -- Check if the written data is the same as the stored.
781 
                  if (hostBaseDeviceId = configDatWrite(15 downto 0)) then
782 
                    -- Same as stored, reset the value to its initial value.
783 
                    hostBaseDeviceIdLocked := '0';
784 
                    hostBaseDeviceId := (others => '1');
785 
                  else
786 
                    -- Not writing the same as the stored value.
787 
                    -- Ignore the write.
788 
                  end if;
789 
                end if;
790 
              end if;
791 
 
792 
              configDatRead(15 downto 0) <= hostBaseDeviceId;
793 
 
794 
            when x"00006C" =>
795 
              -----------------------------------------------------------------
796 
              -- Component TAG CSR.
797 
              -----------------------------------------------------------------
798 
              if (configWe = '1') then
799 
                componentTag := configDatWrite;
800 
              end if;
801 
 
802 
              configDatRead <= componentTag;
803 
 
804 
            when others =>
805 
              -----------------------------------------------------------------
806 
              -- Other access.
807 
              -----------------------------------------------------------------
808 
              -- Respond with all zeros.
809 
              configDatRead <= (others => '0');
810 
          end case;
811 
        end if;
812 
      else
813 
        configAck <= '0';
814 
      end if;
815 
    end if;
816 
  end process;
817 
 
818 39 magro732 
end architecture;
819 6 magro732 
 
820 
 
821 39 magro732 
-------------------------------------------------------------------------------
822 
--
823 
-------------------------------------------------------------------------------
824 
-- REMARK: Extended addresses are not supported yet...
825 
library ieee;
826 
use ieee.std_logic_1164.all;
827 
use ieee.numeric_std.all;
828 
use work.rio_common.all;
829 6 magro732 
 
830 
 
831 39 magro732 
-------------------------------------------------------------------------------
832 
--
833 
-------------------------------------------------------------------------------
834 
entity RequestClassInbound is
835 
  generic(
836 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0);
837 
  port(
838 
    clk : in std_logic;
839 
    areset_n : in std_logic;
840 
    enable : in std_logic;
841 6 magro732 
 
842 39 magro732 
    ready_o : out std_logic;
843 
    vc_o : out std_logic;
844 
    crf_o : out std_logic;
845 
    prio_o : out std_logic_vector(1 downto 0);
846 
    tt_o : out std_logic_vector(1 downto 0);
847 
    dstId_o : out std_logic_vector(31 downto 0);
848 
    srcId_o : out std_logic_vector(31 downto 0);
849 
    tid_o : out std_logic_vector(7 downto 0);
850 
    address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
851 44 magro732 
    length_o : out std_logic_vector(4 downto 0);
852 39 magro732 
    select_o : out std_logic_vector(7 downto 0);
853 
    done_i : in std_logic;
854 
 
855 45 magro732 
    inboundCyc_i : in std_logic;
856 
    inboundStb_i : in std_logic;
857 
    inboundAdr_i : in std_logic_vector(7 downto 0);
858 
    inboundDat_i : in std_logic_vector(31 downto 0);
859 
    inboundAck_o : out std_logic);
860 39 magro732 
end entity;
861 
 
862 
 
863 
-------------------------------------------------------------------------------
864 
--
865 
-------------------------------------------------------------------------------
866 
architecture RequestClassInbound of RequestClassInbound is
867 
  type StateType is (RECEIVE_PACKET, READY);
868 
  signal state : StateType;
869 
 
870 
  signal rdsize : std_logic_vector(3 downto 0);
871 
  signal wdptr : std_logic;
872 
 
873 45 magro732 
  signal inboundAck : std_logic;
874 39 magro732 
  signal complete : std_logic;
875 
 
876 45 magro732 
  signal packetIndex : natural range 0 to 69;
877 39 magro732 
 
878 
begin
879 
 
880 45 magro732 
  inboundAck_o <= inboundAck;
881 39 magro732 
 
882 
  ready_o <= complete when (state = READY) else '0';
883 
 
884 
  RequestClass: process(clk, areset_n)
885 
  begin
886 
    if (areset_n = '0') then
887 44 magro732 
      state <= RECEIVE_PACKET;
888 
 
889 
      rdsize <= (others=>'0');
890 
      wdptr <= '0';
891 
 
892 45 magro732 
      inboundAck <= '0';
893 39 magro732 
      complete <= '0';
894 
 
895 44 magro732 
      packetIndex <= 0;
896 
 
897 39 magro732 
      vc_o <= '0';
898 
      crf_o <= '0';
899 
      prio_o <= "00";
900 
      tt_o <= "00";
901 44 magro732 
      dstId_o <= (others=>'0');
902 
      srcId_o <= (others=>'0');
903 
      tid_o <= (others=>'0');
904 39 magro732 
      address_o <= (others=>'0');
905 
    elsif (clk'event and clk = '1') then
906 
      case state is
907 
        when RECEIVE_PACKET =>
908 
          ---------------------------------------------------------------------
909 
          -- This state waits for a new REQUEST class packet, receives it
910 
          -- and parses it.
911 
          ---------------------------------------------------------------------
912 45 magro732 
          if (inboundCyc_i = '1') then
913 
            if (inboundAck = '0') then
914 
              if (inboundStb_i = '1') then
915 
                if (inboundAdr_i = x"24") then
916 39 magro732 
                  -------------------------------------------------------------
917 
                  -- NREAD packet parser.
918 
                  -------------------------------------------------------------
919 
                  case (packetIndex) is
920 
                    when 0 =>
921 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
922 45 magro732 
                      vc_o <= inboundDat_i(9);
923 
                      crf_o <= inboundDat_i(8);
924 
                      prio_o <= inboundDat_i(7 downto 6);
925 
                      tt_o <= inboundDat_i(5 downto 4);
926 39 magro732 
                      packetIndex <= packetIndex + 1;
927 
                    when 1 =>
928 
                      -- dstid
929 45 magro732 
                      dstId_o <= inboundDat_i;
930 39 magro732 
                      packetIndex <= packetIndex + 1;
931 
                    when 2 =>
932 
                      -- srcid
933 45 magro732 
                      srcId_o <= inboundDat_i;
934 39 magro732 
                      packetIndex <= packetIndex + 1;
935 
                    when 3 =>
936 
                      -- transaction(3:0) & rdsize(3:0) & srcTID(7:0) & address(28:13)
937 45 magro732 
                      rdsize <= inboundDat_i(27 downto 24);
938 
                      tid_o <= inboundDat_i(23 downto 16);
939 
                      address_o(28 downto 13) <= inboundDat_i(15 downto 0);
940 39 magro732 
                      packetIndex <= packetIndex + 1;
941 
                    when 4 =>
942 
                      -- address(12:0) & wdptr & xamsbs(1:0) & crc(15:0)
943 45 magro732 
                      address_o(12 downto 0) <= inboundDat_i(31 downto 19);
944 
                      wdptr <= inboundDat_i(18);
945 
                      address_o(30 downto 29) <= inboundDat_i(17 downto 16);
946 39 magro732 
                      packetIndex <= packetIndex + 1;
947 
                      complete <= '1';
948 
                    when others =>
949 
                      -- There should be no more content in an NREAD.
950 
                      -- Discard.
951 
                  end case;
952 45 magro732 
                  inboundAck <= '1';
953 6 magro732 
                end if;
954 
              end if;
955 
            else
956 45 magro732 
              inboundAck <= '0';
957 6 magro732 
            end if;
958 
          else
959 39 magro732 
            if (complete = '1') then
960 
              state <= READY;
961 6 magro732 
            end if;
962 39 magro732 
            packetIndex <= 0;
963 6 magro732 
          end if;
964 
 
965 39 magro732 
        when READY =>
966 
          ---------------------------------------------------------------------
967 
          -- Wait for the handler of the packet to signal that it has been
968 
          -- processed.
969 
          ---------------------------------------------------------------------
970 
          if (done_i = '1') then
971 
            complete <= '0';
972 
            state <= RECEIVE_PACKET;
973 6 magro732 
          end if;
974 
 
975 39 magro732 
        when others =>
976 
          ---------------------------------------------------------------------
977 
          --
978 
          ---------------------------------------------------------------------
979 6 magro732 
 
980 39 magro732 
      end case;
981 
    end if;
982 
  end process;
983 
 
984 
  -----------------------------------------------------------------------------
985 
  -- Transformation of rdsize and wdptr into length of access and byte lanes.
986 
  -----------------------------------------------------------------------------
987 
 
988 
  process(clk, areset_n)
989 
  begin
990 
    if (areset_n = '0') then
991 44 magro732 
      length_o <= "00000";
992 39 magro732 
      select_o <= (others=>'0');
993 
    elsif (clk'event and clk = '1') then
994 
      if (complete = '1') then
995 
        if (wdptr = '0') then
996 
          case rdsize is
997 
            when "0000" =>
998 44 magro732 
              length_o <= "00000";
999 39 magro732 
              select_o <= "10000000";
1000 
            when "0001" =>
1001 44 magro732 
              length_o <= "00000";
1002 39 magro732 
              select_o <= "01000000";
1003 
            when "0010" =>
1004 44 magro732 
              length_o <= "00000";
1005 39 magro732 
              select_o <= "00100000";
1006 
            when "0011" =>
1007 44 magro732 
              length_o <= "00000";
1008 39 magro732 
              select_o <= "00010000";
1009 
            when "0100" =>
1010 44 magro732 
              length_o <= "00000";
1011 39 magro732 
              select_o <= "11000000";
1012 
            when "0101" =>
1013 44 magro732 
              length_o <= "00000";
1014 39 magro732 
              select_o <= "11100000";
1015 
            when "0110" =>
1016 44 magro732 
              length_o <= "00000";
1017 39 magro732 
              select_o <= "00110000";
1018 
            when "0111" =>
1019 44 magro732 
              length_o <= "00000";
1020 39 magro732 
              select_o <= "11111000";
1021 
            when "1000" =>
1022 44 magro732 
              length_o <= "00000";
1023 39 magro732 
              select_o <= "11110000";
1024 
            when "1001" =>
1025 44 magro732 
              length_o <= "00000";
1026 39 magro732 
              select_o <= "11111100";
1027 
            when "1010" =>
1028 44 magro732 
              length_o <= "00000";
1029 39 magro732 
              select_o <= "11111110";
1030 
            when "1011" =>
1031 44 magro732 
              length_o <= "00000";
1032 39 magro732 
              select_o <= "11111111";
1033 
            when "1100" =>
1034 44 magro732 
              length_o <= "00011";
1035 39 magro732 
              select_o <= "11111111";
1036 
            when "1101" =>
1037 44 magro732 
              length_o <= "01011";
1038 39 magro732 
              select_o <= "11111111";
1039 
            when "1110" =>
1040 44 magro732 
              length_o <= "10011";
1041 39 magro732 
              select_o <= "11111111";
1042 
            when others =>
1043 44 magro732 
              length_o <= "11011";
1044 39 magro732 
              select_o <= "11111111";
1045 
          end case;
1046 
        else
1047 
          case rdsize is
1048 
            when "0000" =>
1049 44 magro732 
              length_o <= "00000";
1050 39 magro732 
              select_o <= "00001000";
1051 
            when "0001" =>
1052 44 magro732 
              length_o <= "00000";
1053 39 magro732 
              select_o <= "00000100";
1054 
            when "0010" =>
1055 44 magro732 
              length_o <= "00000";
1056 39 magro732 
              select_o <= "00000010";
1057 
            when "0011" =>
1058 44 magro732 
              length_o <= "00000";
1059 39 magro732 
              select_o <= "00000001";
1060 
            when "0100" =>
1061 44 magro732 
              length_o <= "00000";
1062 39 magro732 
              select_o <= "00001100";
1063 
            when "0101" =>
1064 44 magro732 
              length_o <= "00000";
1065 39 magro732 
              select_o <= "00000111";
1066 
            when "0110" =>
1067 44 magro732 
              length_o <= "00000";
1068 39 magro732 
              select_o <= "00000011";
1069 
            when "0111" =>
1070 44 magro732 
              length_o <= "00000";
1071 39 magro732 
              select_o <= "00011111";
1072 
            when "1000" =>
1073 44 magro732 
              length_o <= "00000";
1074 39 magro732 
              select_o <= "00001111";
1075 
            when "1001" =>
1076 44 magro732 
              length_o <= "00000";
1077 39 magro732 
              select_o <= "00111111";
1078 
            when "1010" =>
1079 44 magro732 
              length_o <= "00000";
1080 39 magro732 
              select_o <= "01111111";
1081 
            when "1011" =>
1082 44 magro732 
              length_o <= "00001";
1083 39 magro732 
              select_o <= "11111111";
1084 
            when "1100" =>
1085 44 magro732 
              length_o <= "00111";
1086 39 magro732 
              select_o <= "11111111";
1087 
            when "1101" =>
1088 44 magro732 
              length_o <= "01111";
1089 39 magro732 
              select_o <= "11111111";
1090 
            when "1110" =>
1091 44 magro732 
              length_o <= "10111";
1092 39 magro732 
              select_o <= "11111111";
1093 
            when others =>
1094 44 magro732 
              length_o <= "11111";
1095 39 magro732 
              select_o <= "11111111";
1096 
          end case;
1097 
        end if;
1098 
      end if;
1099 
    end if;
1100 
  end process;
1101 
 
1102 
end architecture;
1103 
 
1104 
 
1105 
-------------------------------------------------------------------------------
1106 
--
1107 
-------------------------------------------------------------------------------
1108 
library ieee;
1109 
use ieee.std_logic_1164.all;
1110 
use ieee.numeric_std.all;
1111 
use work.rio_common.all;
1112 
 
1113 
 
1114 
-------------------------------------------------------------------------------
1115 
--
1116 
-------------------------------------------------------------------------------
1117 
entity WriteClassInbound is
1118 
  generic(
1119 
    EXTENDED_ADDRESS : natural range 0 to 2 := 0);
1120 
  port(
1121 
    clk : in std_logic;
1122 
    areset_n : in std_logic;
1123 
    enable : in std_logic;
1124 
 
1125 
    ready_o : out std_logic;
1126 45 magro732 
    responseNeeded_o : out std_logic;
1127 39 magro732 
    vc_o : out std_logic;
1128 
    crf_o : out std_logic;
1129 
    prio_o : out std_logic_vector(1 downto 0);
1130 
    tt_o : out std_logic_vector(1 downto 0);
1131 
    dstId_o : out std_logic_vector(31 downto 0);
1132 
    srcId_o : out std_logic_vector(31 downto 0);
1133 
    tid_o : out std_logic_vector(7 downto 0);
1134 
    address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
1135 44 magro732 
    length_o : out std_logic_vector(4 downto 0);
1136 39 magro732 
    select_o : out std_logic_vector(7 downto 0);
1137 44 magro732 
    payloadRead_i : in std_logic;
1138 
    payloadIndex_i : in std_logic_vector(4 downto 0);
1139 
    payload_o : out std_logic_vector(63 downto 0);
1140 39 magro732 
    done_i : in std_logic;
1141 
 
1142 45 magro732 
    inboundCyc_i : in std_logic;
1143 
    inboundStb_i : in std_logic;
1144 
    inboundAdr_i : in std_logic_vector(7 downto 0);
1145 
    inboundDat_i : in std_logic_vector(31 downto 0);
1146 
    inboundAck_o : out std_logic);
1147 39 magro732 
end entity;
1148 
 
1149 
 
1150 
-------------------------------------------------------------------------------
1151 
--
1152 
-------------------------------------------------------------------------------
1153 
architecture WriteClassInbound of WriteClassInbound is
1154 
  component MemorySimpleDualPort
1155 
    generic(
1156 
      ADDRESS_WIDTH : natural := 1;
1157 
      DATA_WIDTH : natural := 1);
1158 
    port(
1159 
      clkA_i : in std_logic;
1160 
      enableA_i : in std_logic;
1161 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1162 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1163 
 
1164 
      clkB_i : in std_logic;
1165 
      enableB_i : in std_logic;
1166 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1167 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1168 
  end component;
1169 
 
1170 
  type StateType is (RECEIVE_PACKET, READY);
1171 
  signal state : StateType;
1172 
 
1173 
  signal wdptr : std_logic;
1174 
  signal wrsize : std_logic_vector(3 downto 0);
1175 
 
1176 45 magro732 
  signal inboundAck : std_logic;
1177 39 magro732 
  signal complete : std_logic;
1178 
 
1179 45 magro732 
  signal packetIndex : natural range 0 to 69;
1180 39 magro732 
 
1181 44 magro732 
  signal doubleWord : std_logic_vector(63 downto 16);
1182 
 
1183 39 magro732 
  signal memoryWrite : std_logic;
1184 
  signal memoryAddress : std_logic_vector(4 downto 0);
1185 
  signal memoryDataIn : std_logic_vector(63 downto 0);
1186 
 
1187 44 magro732 
 
1188 39 magro732 
begin
1189 
 
1190 45 magro732 
  inboundAck_o <= inboundAck;
1191 39 magro732 
 
1192 
  ready_o <= complete when (state = READY) else '0';
1193 
 
1194 
  WriteClass: process(clk, areset_n)
1195 
  begin
1196 
    if (areset_n = '0') then
1197 44 magro732 
      state <= RECEIVE_PACKET;
1198 
 
1199 
      wdptr <= '0';
1200 
      wrsize <= (others=>'0');
1201 
 
1202 45 magro732 
      inboundAck <= '0';
1203 39 magro732 
      complete <= '0';
1204 45 magro732 
      responseNeeded_o <= '0';
1205 39 magro732 
 
1206 44 magro732 
      packetIndex <= 0;
1207 
      doubleWord <= (others=>'0');
1208 
 
1209 
      memoryWrite <= '0';
1210 
      memoryAddress <= (others=>'0');
1211 
      memoryDataIn <= (others=>'0');
1212 
 
1213 39 magro732 
      vc_o <= '0';
1214 
      crf_o <= '0';
1215 
      prio_o <= "00";
1216 
      tt_o <= "00";
1217 44 magro732 
      dstId_o <= (others=>'0');
1218 
      srcId_o <= (others=>'0');
1219 39 magro732 
      tid_o <= (others=>'0');
1220 
      address_o <= (others=>'0');
1221 
    elsif (clk'event and clk = '1') then
1222 
      case state is
1223 
        when RECEIVE_PACKET =>
1224 45 magro732 
          if (inboundCyc_i = '1') then
1225 
            if (inboundAck = '0') then
1226 
              if (inboundStb_i = '1') then
1227 
                if ((inboundAdr_i = x"55") or (inboundAdr_i = x"54")) then
1228 39 magro732 
                  -------------------------------------------------------------
1229 45 magro732 
                  -- NWRITE/NWRITER packet parser.
1230 39 magro732 
                  -------------------------------------------------------------
1231 
                  case (packetIndex) is
1232 
                    when 0 =>
1233 
                      -- x"0000" & ackid & vc & crf & prio & tt & ftype
1234 45 magro732 
                      vc_o <= inboundDat_i(9);
1235 
                      crf_o <= inboundDat_i(8);
1236 
                      prio_o <= inboundDat_i(7 downto 6);
1237 
                      tt_o <= inboundDat_i(5 downto 4);
1238 39 magro732 
                      packetIndex <= packetIndex + 1;
1239 
                    when 1 =>
1240 
                      -- destId
1241 45 magro732 
                      dstId_o <= inboundDat_i;
1242 39 magro732 
                      packetIndex <= packetIndex + 1;
1243 
                    when 2 =>
1244 
                      -- srcId
1245 45 magro732 
                      srcId_o <= inboundDat_i;
1246 39 magro732 
                      packetIndex <= packetIndex + 1;
1247 
                    when 3 =>
1248 
                      -- transaction & wrsize & srcTID & address(28:13)
1249 
                      -- REMARK: Add support for extended addresses here...
1250 45 magro732 
                      if (inboundDat_i(31 downto 28) = "0101") then
1251 
                        responseNeeded_o <= '1';
1252 
                      else
1253 
                        responseNeeded_o <= '0';
1254 
                      end if;
1255 
                      wrsize <= inboundDat_i(27 downto 24);
1256 
                      tid_o <= inboundDat_i(23 downto 16);
1257 
                      address_o(28 downto 13) <= inboundDat_i(15 downto 0);
1258 39 magro732 
                      packetIndex <= packetIndex + 1;
1259 
                    when 4 =>
1260 
                      -- address(12:0) & wdptr & xamsbs(1:0) & double-word(63:48)
1261 45 magro732 
                      address_o(12 downto 0) <= inboundDat_i(31 downto 19);
1262 
                      wdptr <= inboundDat_i(18);
1263 
                      address_o(30 downto 29) <= inboundDat_i(17 downto 16);
1264 
                      doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
1265 39 magro732 
                      packetIndex <= packetIndex + 1;
1266 
                    when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31  | 33 | 35 |
1267 
                      37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
1268 
                      -- double-word(47:16)
1269 45 magro732 
                      doubleWord(47 downto 16) <= inboundDat_i;
1270 39 magro732 
                      packetIndex <= packetIndex + 1;
1271 
                    when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32  | 34 |
1272 45 magro732 
                      36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 | 68 =>
1273 39 magro732 
                      -- double-word(15:0) & double-word(63:48)
1274 45 magro732 
                      doubleWord(63 downto 48) <= inboundDat_i(15 downto 0);
1275 39 magro732 
                      packetIndex <= packetIndex + 1;
1276 
 
1277 
                      memoryWrite <= '1';
1278 45 magro732 
                      memoryDataIn <= doubleWord(63 downto 16) & inboundDat_i(31 downto 16);
1279 39 magro732 
                    when others =>
1280 45 magro732 
                      -- There should be no more content in an NWRITE/NWRITER request.
1281 39 magro732 
                      -- Discard.
1282 
                  end case;
1283 45 magro732 
                  inboundAck <= '1';
1284 6 magro732 
                end if;
1285 
              end if;
1286 
            else
1287 39 magro732 
              if (memoryWrite = '1') then
1288 
                memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
1289 
              end if;
1290 
 
1291 
              memoryWrite <= '0';
1292 45 magro732 
              inboundAck <= '0';
1293 6 magro732 
            end if;
1294 
          else
1295 45 magro732 
            if (packetIndex >= 6) then
1296 
              complete <= '1';
1297 39 magro732 
              state <= READY;
1298 45 magro732 
            else
1299 
              packetIndex <= 0;
1300 
              memoryAddress <= (others=>'0');
1301 39 magro732 
            end if;
1302 6 magro732 
          end if;
1303 
 
1304 39 magro732 
        when READY =>
1305 
          ---------------------------------------------------------------------
1306 
          -- Wait for the handler of the packet to signal that it has been
1307 
          -- processed.
1308 
          ---------------------------------------------------------------------
1309 
          if (done_i = '1') then
1310 45 magro732 
            packetIndex <= 0;
1311 
            memoryAddress <= (others=>'0');
1312 39 magro732 
            complete <= '0';
1313 
            state <= RECEIVE_PACKET;
1314 6 magro732 
          end if;
1315 
 
1316 
        when others =>
1317 39 magro732 
          ---------------------------------------------------------------------
1318 
          --
1319 
          ---------------------------------------------------------------------
1320 6 magro732 
 
1321 
      end case;
1322 39 magro732 
    end if;
1323 
  end process;
1324 6 magro732 
 
1325 39 magro732 
  -----------------------------------------------------------------------------
1326 
  -- Transformation of wrsize and wdptr into length of access and byte lanes.
1327 
  -----------------------------------------------------------------------------
1328 
 
1329 
  process(clk, areset_n)
1330 
  begin
1331 
    if (areset_n = '0') then
1332 44 magro732 
      length_o <= "00000";
1333 39 magro732 
      select_o <= (others=>'0');
1334 
    elsif (clk'event and clk = '1') then
1335 
      if (complete = '1') then
1336 
        if (wdptr = '0') then
1337 
          case wrsize is
1338 
            when "0000" =>
1339 44 magro732 
              length_o <= "00000";
1340 39 magro732 
              select_o <= "10000000";
1341 
            when "0001" =>
1342 44 magro732 
              length_o <= "00000";
1343 39 magro732 
              select_o <= "01000000";
1344 
            when "0010" =>
1345 44 magro732 
              length_o <= "00000";
1346 39 magro732 
              select_o <= "00100000";
1347 
            when "0011" =>
1348 44 magro732 
              length_o <= "00000";
1349 39 magro732 
              select_o <= "00010000";
1350 
            when "0100" =>
1351 44 magro732 
              length_o <= "00000";
1352 39 magro732 
              select_o <= "11000000";
1353 
            when "0101" =>
1354 44 magro732 
              length_o <= "00000";
1355 39 magro732 
              select_o <= "11100000";
1356 
            when "0110" =>
1357 44 magro732 
              length_o <= "00000";
1358 39 magro732 
              select_o <= "00110000";
1359 
            when "0111" =>
1360 44 magro732 
              length_o <= "00000";
1361 39 magro732 
              select_o <= "11111000";
1362 
            when "1000" =>
1363 44 magro732 
              length_o <= "00000";
1364 39 magro732 
              select_o <= "11110000";
1365 
            when "1001" =>
1366 44 magro732 
              length_o <= "00000";
1367 39 magro732 
              select_o <= "11111100";
1368 
            when "1010" =>
1369 44 magro732 
              length_o <= "00000";
1370 39 magro732 
              select_o <= "11111110";
1371 
            when "1011" =>
1372 44 magro732 
              length_o <= "00000";
1373 39 magro732 
              select_o <= "11111111";
1374 
            when others =>
1375 45 magro732 
              length_o <= std_logic_vector(unsigned(memoryAddress)-1);
1376 39 magro732 
              select_o <= "11111111";
1377 
          end case;
1378 
        else
1379 
          case wrsize is
1380 
            when "0000" =>
1381 44 magro732 
              length_o <= "00000";
1382 39 magro732 
              select_o <= "00001000";
1383 
            when "0001" =>
1384 44 magro732 
              length_o <= "00000";
1385 39 magro732 
              select_o <= "00000100";
1386 
            when "0010" =>
1387 44 magro732 
              length_o <= "00000";
1388 39 magro732 
              select_o <= "00000010";
1389 
            when "0011" =>
1390 44 magro732 
              length_o <= "00000";
1391 39 magro732 
              select_o <= "00000001";
1392 
            when "0100" =>
1393 44 magro732 
              length_o <= "00000";
1394 39 magro732 
              select_o <= "00001100";
1395 
            when "0101" =>
1396 44 magro732 
              length_o <= "00000";
1397 39 magro732 
              select_o <= "00000111";
1398 
            when "0110" =>
1399 44 magro732 
              length_o <= "00000";
1400 39 magro732 
              select_o <= "00000011";
1401 
            when "0111" =>
1402 44 magro732 
              length_o <= "00000";
1403 39 magro732 
              select_o <= "00011111";
1404 
            when "1000" =>
1405 44 magro732 
              length_o <= "00000";
1406 39 magro732 
              select_o <= "00001111";
1407 
            when "1001" =>
1408 44 magro732 
              length_o <= "00000";
1409 39 magro732 
              select_o <= "00111111";
1410 
            when "1010" =>
1411 44 magro732 
              length_o <= "00000";
1412 39 magro732 
              select_o <= "01111111";
1413 
            when others =>
1414 45 magro732 
              length_o <= std_logic_vector(unsigned(memoryAddress)-1);
1415 39 magro732 
              select_o <= "11111111";
1416 
          end case;
1417 
        end if;
1418 
      end if;
1419 6 magro732 
    end if;
1420 39 magro732 
  end process;
1421 6 magro732 
 
1422 
  -----------------------------------------------------------------------------
1423 39 magro732 
  -- Payload content memory.
1424 6 magro732 
  -----------------------------------------------------------------------------
1425 44 magro732 
 
1426 39 magro732 
  PayloadMemory: MemorySimpleDualPort
1427 
    generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
1428 
    port map(clkA_i=>clk,
1429 
             enableA_i=>memoryWrite,
1430 
             addressA_i=>memoryAddress,
1431 
             dataA_i=>memoryDataIn,
1432 
             clkB_i=>clk,
1433 44 magro732 
             enableB_i=>payloadRead_i,
1434 
             addressB_i=>payloadIndex_i,
1435 39 magro732 
             dataB_o=>payload_o);
1436 6 magro732 
 
1437 39 magro732 
end architecture;
1438 
 
1439 
 
1440 
 
1441 
-------------------------------------------------------------------------------
1442 
--
1443 
-------------------------------------------------------------------------------
1444 
library ieee;
1445 
use ieee.std_logic_1164.all;
1446 
use ieee.numeric_std.all;
1447 
use work.rio_common.all;
1448 
 
1449 
-------------------------------------------------------------------------------
1450 
--
1451 
-------------------------------------------------------------------------------
1452 
entity ResponseClassOutbound is
1453 
  port(
1454 
    clk : in std_logic;
1455 
    areset_n : in std_logic;
1456 
    enable : in std_logic;
1457 
 
1458 
    ready_i : in std_logic;
1459 
    vc_i : in std_logic;
1460 
    crf_i : in std_logic;
1461 
    prio_i : in std_logic_vector(1 downto 0);
1462 
    tt_i : in std_logic_vector(1 downto 0);
1463 
    dstid_i : in std_logic_vector(31 downto 0);
1464 
    srcid_i : in std_logic_vector(31 downto 0);
1465 
    tid_i : in std_logic_vector(7 downto 0);
1466 
    error_i : in std_logic;
1467 
    payloadPresent_i :  in std_logic;
1468 44 magro732 
    payloadLength_i : in std_logic_vector(4 downto 0);
1469 39 magro732 
    payloadWrite_i : in std_logic;
1470 44 magro732 
    payloadIndex_i : in std_logic_vector(4 downto 0);
1471 
    payload_i : in std_logic_vector(63 downto 0);
1472 39 magro732 
    done_o : out std_logic;
1473 
 
1474 45 magro732 
    outboundCyc_o : out std_logic;
1475 
    outboundStb_o : out std_logic;
1476 
    outboundDat_o : out std_logic_vector(31 downto 0);
1477 
    outboundAck_i : in std_logic);
1478 39 magro732 
end entity;
1479 
 
1480 
 
1481 
-------------------------------------------------------------------------------
1482 
--
1483 
-------------------------------------------------------------------------------
1484 
architecture ResponseClassOutbound of ResponseClassOutbound is
1485 
  component MemorySimpleDualPort
1486 
    generic(
1487 
      ADDRESS_WIDTH : natural := 1;
1488 
      DATA_WIDTH : natural := 1);
1489 
    port(
1490 
      clkA_i : in std_logic;
1491 
      enableA_i : in std_logic;
1492 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1493 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1494 
 
1495 
      clkB_i : in std_logic;
1496 
      enableB_i : in std_logic;
1497 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1498 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1499 
  end component;
1500 
 
1501 44 magro732 
  signal header : std_logic_vector(31 downto 0);
1502 
 
1503 
  type StateType is (WAIT_PACKET, SEND_RESPONSE,
1504 39 magro732 
                     WAIT_COMPLETE, RESPONSE_DONE);
1505 
  signal state : StateType;
1506 
 
1507 44 magro732 
  signal packetIndex : natural range 0 to 68;
1508 
 
1509 
  signal responsePayloadIndex : std_logic_vector(4 downto 0);
1510 
  signal responsePayload : std_logic_vector(15 downto 0);
1511 39 magro732 
 
1512 
  signal memoryEnable : std_logic;
1513 
  signal memoryAddress : std_logic_vector(4 downto 0);
1514 
  signal memoryDataRead : std_logic_vector(63 downto 0);
1515 
 
1516 
begin
1517 
 
1518 
  header <= x"0000" & "000000" & vc_i & crf_i & prio_i & tt_i & x"d";
1519 
 
1520 
  Response: process(clk, areset_n)
1521 
  begin
1522 
    if (areset_n = '0') then
1523 44 magro732 
      state <= WAIT_PACKET;
1524 39 magro732 
 
1525 44 magro732 
      packetIndex <= 0;
1526 
 
1527 
      responsePayloadIndex <= (others=>'0');
1528 
      responsePayload <= (others=>'0');
1529 
 
1530 39 magro732 
      memoryEnable <= '0';
1531 
      memoryAddress <= (others=>'0');
1532 
 
1533 
      done_o <= '0';
1534 
 
1535 45 magro732 
      outboundCyc_o <= '0';
1536 
      outboundStb_o <= '0';
1537 
      outboundDat_o <= (others=>'0');
1538 39 magro732 
    elsif (clk'event and clk = '1') then
1539 
      if (enable = '1') then
1540 
        case state is
1541 
          when WAIT_PACKET =>
1542 
            -------------------------------------------------------------------
1543 
            --
1544 
            -------------------------------------------------------------------
1545 
            if (ready_i = '1') then
1546 45 magro732 
              outboundCyc_o <= '1';
1547 
              outboundStb_o <= '1';
1548 
              outboundDat_o <= header;
1549 39 magro732 
 
1550 
              packetIndex <= 1;
1551 44 magro732 
              responsePayloadIndex <= (others=>'0');
1552 39 magro732 
 
1553 
              memoryEnable <= '1';
1554 
              memoryAddress <= (others=>'0');
1555 
 
1556 
              state <= SEND_RESPONSE;
1557 6 magro732 
            end if;
1558 39 magro732 
 
1559 
          when SEND_RESPONSE =>
1560 
            ---------------------------------------------------------------------
1561 
            --
1562 
            ---------------------------------------------------------------------
1563 45 magro732 
            if (outboundAck_i = '1') then
1564 39 magro732 
              case (packetIndex) is
1565 
                when 1 =>
1566 
                  -- destination
1567 45 magro732 
                  outboundDat_o <= dstId_i;
1568 39 magro732 
                  packetIndex <= packetIndex + 1;
1569 
                when 2 =>
1570 
                  -- source
1571 45 magro732 
                  outboundDat_o <= srcId_i;
1572 39 magro732 
                  packetIndex <= packetIndex + 1;
1573 
                when 3 =>
1574 
                  -- transaction & status & targetTID & double-word0(63:48)
1575 
                  if (error_i = '0') then
1576 
                    if (payloadPresent_i = '0') then
1577 45 magro732 
                      outboundDat_o <= "0000" & "0000" & tid_i & x"0000";
1578 39 magro732 
                      state <= WAIT_COMPLETE;
1579 
                    else
1580 45 magro732 
                      outboundDat_o <= "1000" & "0000" & tid_i & memoryDataRead(63 downto 48);
1581 39 magro732 
                    end if;
1582 
                  else
1583 45 magro732 
                    outboundDat_o <= "0000" & "0111" & tid_i & x"0000";
1584 39 magro732 
                    state <= WAIT_COMPLETE;
1585 
                  end if;
1586 
                  packetIndex <= packetIndex + 1;
1587 
                when 4 | 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 | 34 |
1588 
                  36 | 38 | 40 | 42 | 44 | 46 | 48 | 50 | 52 | 54 | 56 | 58 | 60 | 62 | 64 | 66 =>
1589 
                  -- double-wordN(47:16)
1590 45 magro732 
                  outboundDat_o <= memoryDataRead(47 downto 16);
1591 39 magro732 
                  responsePayload <= memoryDataRead(15 downto 0);
1592 
                  memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
1593 
                  packetIndex <= packetIndex + 1;
1594 
                when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
1595 
                  37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
1596 
                  -- double-wordN(15:0) & double-wordN(63:48)
1597 45 magro732 
                  outboundDat_o <= responsePayload & memoryDataRead(63 downto 48);
1598 39 magro732 
                  packetIndex <= packetIndex + 1;
1599 
 
1600 
                  responsePayloadIndex <=
1601 
                    std_logic_vector(unsigned(responsePayloadIndex) + 1);
1602 
 
1603 44 magro732 
                  if (responsePayloadIndex = payloadLength_i) then
1604 39 magro732 
                    state <= WAIT_COMPLETE;
1605 
                  else
1606 
                    packetIndex <= packetIndex + 1;
1607 
                  end if;
1608 
                when others =>
1609 
                  -- Unallowed response length.
1610 
                  -- Dont do anything.
1611 
              end case;
1612 6 magro732 
            end if;
1613 39 magro732 
 
1614 
          when WAIT_COMPLETE =>
1615 
            -------------------------------------------------------------------
1616 
            --
1617 
            -------------------------------------------------------------------
1618 45 magro732 
            if (outboundAck_i = '1') then
1619 
              outboundCyc_o <= '0';
1620 
              outboundStb_o <= '0';
1621 39 magro732 
              state <= RESPONSE_DONE;
1622 
            end if;
1623 
 
1624 
          when RESPONSE_DONE =>
1625 
            ---------------------------------------------------------------------
1626 
            --
1627 
            ---------------------------------------------------------------------
1628 
            memoryEnable <= '0';
1629 
            if (ready_i = '0') then
1630 
              state <= WAIT_PACKET;
1631 
              done_o <= '0';
1632 6 magro732 
            else
1633 39 magro732 
              done_o <= '1';
1634 6 magro732 
            end if;
1635 39 magro732 
 
1636 6 magro732 
          when others =>
1637 39 magro732 
            ---------------------------------------------------------------------
1638 
            --
1639 
            ---------------------------------------------------------------------
1640 
            state <= WAIT_PACKET;
1641 
 
1642 6 magro732 
        end case;
1643 
      end if;
1644 
    end if;
1645 
  end process;
1646 
 
1647 
  -----------------------------------------------------------------------------
1648 39 magro732 
  -- Payload content memory.
1649 6 magro732 
  -----------------------------------------------------------------------------
1650 39 magro732 
  PayloadMemory: MemorySimpleDualPort
1651 
    generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
1652 
    port map(clkA_i=>clk,
1653 
             enableA_i=>payloadWrite_i,
1654 
             addressA_i=>payloadIndex_i,
1655 
             dataA_i=>payload_i,
1656 
             clkB_i=>clk,
1657 
             enableB_i=>memoryEnable,
1658 
             addressB_i=>memoryAddress,
1659 
             dataB_o=>memoryDataRead);
1660 6 magro732 
 
1661 
end architecture;

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