URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [.gitignore] - Blame information for rev 4


*.sdf
*.opensdf
*.suo
*.err
Debug
!src/common/debug
Release
*.log
*.rcc
*.pyc
linuxbuild
win32build
win64build
moc_*.h

Line No.	Rev	Author	Line
1	4	sergeykhbr	`*.sdf`
2			`*.opensdf`
3			`*.suo`
4			`*.err`
5			`Debug`
6			`!src/common/debug`
7			`Release`
8			`*.log`
9			`*.rcc`
10			`*.pyc`
11			`linuxbuild`
12			`win32build`
13			`win64build`
14			`moc_*.h`