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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_fnc_plugin/] [riscv-ext-m.cpp] - Blame information for rev 2

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1 2 sergeykhbr 
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      RISC-V extension-M.
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 */
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#include "api_utils.h"
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#include "riscv-isa.h"
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#include "instructions.h"
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namespace debugger {
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/**
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 * @brief The DIV signed division
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 */
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class DIV : public IsaProcessor {
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public:
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    DIV() : IsaProcessor("DIV", "0000001??????????100?????0110011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        if (data->regs[u.bits.rs2]) {
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            data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
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                 / static_cast<int64_t>(data->regs[u.bits.rs2]);
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        } else {
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            data->regs[u.bits.rd] = 0;
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        }
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief DIVU unsigned division
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 */
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class DIVU : public IsaProcessor {
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public:
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    DIVU() : IsaProcessor("DIVU", "0000001??????????101?????0110011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        if (data->regs[u.bits.rs2]) {
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            data->regs[u.bits.rd] =
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                data->regs[u.bits.rs1] / data->regs[u.bits.rs2];
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        } else {
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            data->regs[u.bits.rd] = 0;
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        }
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief DIVUW 32-bits unsigned division (RV64I)
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 */
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class DIVUW : public IsaProcessor {
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public:
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    DIVUW() : IsaProcessor("DIVUW", "0000001??????????101?????0111011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        if (static_cast<uint32_t>(data->regs[u.bits.rs2])) {
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            data->regs[u.bits.rd] =
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                static_cast<uint32_t>(data->regs[u.bits.rs1]) /
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                static_cast<uint32_t>(data->regs[u.bits.rs2]);
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        } else {
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            data->regs[u.bits.rd] = 0;
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        }
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief DIVW 32-bits signed division (RV64I)
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 */
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class DIVW : public IsaProcessor {
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public:
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    DIVW() : IsaProcessor("DIVW", "0000001??????????100?????0111011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        int32_t divident = static_cast<int32_t>(data->regs[u.bits.rs1]);
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        int32_t divisor = static_cast<int32_t>(data->regs[u.bits.rs2]);
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        if (divisor) {
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            data->regs[u.bits.rd] = static_cast<int64_t>(divident / divisor);
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        } else {
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            data->regs[u.bits.rd] = 0;
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        }
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief The MUL signed multiplication
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 *
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 * MUL performs an XLEN-bit XLEN-bit multiplication and places the lower XLEN
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 * bits in the destination register.
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 */
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class MUL : public IsaProcessor {
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public:
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    MUL() : IsaProcessor("MUL", "0000001??????????000?????0110011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
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                * static_cast<int64_t>(data->regs[u.bits.rs2]);
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief The MULW 32-bits signed multiplication (RV64I)
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 *
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 * MULW is only valid for RV64, and multiplies the lower 32 bits of the source
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 * registers, placing the sign-extension of the lower 32 bits of the result
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 * into the destination register. MUL can be used to obtain the upper 32 bits
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 * of the 64-bit product, but signed arguments must be proper 32-bit signed
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 * values, whereas unsigned arguments must have their upper 32 bits clear.
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 */
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class MULW : public IsaProcessor {
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public:
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    MULW() : IsaProcessor("MULW", "0000001??????????000?????0111011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        int32_t m1 = static_cast<int32_t>(data->regs[u.bits.rs1]);
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        int32_t m2 = static_cast<int32_t>(data->regs[u.bits.rs2]);
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        data->regs[u.bits.rd] = static_cast<int64_t>(m1 * m2);
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        if (data->regs[u.bits.rd] & (1LL << 31)) {
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            data->regs[u.bits.rd] |= EXT_SIGN_32;
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        }
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief The REM (remainder of the corresponding signed division operation)
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 */
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class REM : public IsaProcessor {
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public:
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    REM() : IsaProcessor("REM", "0000001??????????110?????0110011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        data->regs[u.bits.rd] = static_cast<int64_t>(data->regs[u.bits.rs1])
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             % static_cast<int64_t>(data->regs[u.bits.rs2]);
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief The REMU (remainder of the corresponding unsgined division operation)
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 */
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class REMU : public IsaProcessor {
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public:
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    REMU() : IsaProcessor("REMU", "0000001??????????111?????0110011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        u.value = payload[0];
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        data->regs[u.bits.rd] =
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            data->regs[u.bits.rs1] % data->regs[u.bits.rs2];
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        data->npc = data->pc + 4;
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    }
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};
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/**
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 * @brief REMW signed reminder operation
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 *
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 * REMW and REMUW instructions are only valid
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 * for RV64, and provide the corresponding signed and unsigned remainder
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 * operations respectively.
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 * Both REMW and REMUW sign-extend the 32-bit result to 64 bits.
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 */
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class REMW : public IsaProcessor {
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public:
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    REMW() : IsaProcessor("REMW", "0000001??????????110?????0111011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        int32_t tmp;
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        u.value = payload[0];
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        tmp = static_cast<int32_t>(data->regs[u.bits.rs1])
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            % static_cast<int32_t>(data->regs[u.bits.rs2]);
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        data->regs[u.bits.rd] =
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            static_cast<uint64_t>(static_cast<int64_t>(tmp));
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        data->npc = data->pc + 4;
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    }
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};
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class REMUW : public IsaProcessor {
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public:
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    REMUW() : IsaProcessor("REMUW", "0000001??????????111?????0111011") {}
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    virtual void exec(uint32_t *payload, CpuContextType *data) {
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        ISA_R_type u;
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        uint32_t tmp;
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        u.value = payload[0];
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        tmp = static_cast<uint32_t>(data->regs[u.bits.rs1])
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            % static_cast<uint32_t>(data->regs[u.bits.rs2]);
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        data->regs[u.bits.rd] =
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            static_cast<uint64_t>(static_cast<int64_t>(tmp));
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        data->npc = data->pc + 4;
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    }
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};
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void addIsaExtensionM(CpuContextType *data, AttributeType *out) {
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    addSupportedInstruction(new DIV, out);
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    addSupportedInstruction(new DIVU, out);
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    addSupportedInstruction(new DIVUW, out);
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    addSupportedInstruction(new DIVW, out);
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    addSupportedInstruction(new MUL, out);
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    addSupportedInstruction(new MULW, out);
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    addSupportedInstruction(new REM, out);
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    addSupportedInstruction(new REMU, out);
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    addSupportedInstruction(new REMW, out);
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    addSupportedInstruction(new REMUW, out);
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    // TODO
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    /*
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    addInstr("MULH",               "0000001??????????001?????0110011", NULL, out);
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    addInstr("MULHSU",             "0000001??????????010?????0110011", NULL, out);
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    addInstr("MULHU",              "0000001??????????011?????0110011", NULL, out);
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    */
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    data->csr[CSR_misa] |= (1LL << ('M' - 'A'));
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}
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}  // namespace debugger

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