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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [cache/] [cache_top.cpp] - Blame information for rev 3

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Line No. Rev Author Line
1 3 sergeykhbr 
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      Memory Cache Top level.
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 */
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#include "cache_top.h"
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namespace debugger {
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CacheTop::CacheTop(sc_module_name name_) : sc_module(name_) {
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    SC_METHOD(comb);
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    sensitive << i_nrst;
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    sensitive << i_req_mem_ready;
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    sensitive << i.req_mem_valid;
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    sensitive << i.req_mem_write;
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    sensitive << i.req_mem_addr;
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    sensitive << i.req_mem_strob;
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    sensitive << i.req_mem_wdata;
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    sensitive << d.req_mem_valid;
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    sensitive << d.req_mem_write;
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    sensitive << d.req_mem_addr;
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    sensitive << d.req_mem_strob;
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    sensitive << d.req_mem_wdata;
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    sensitive << i_resp_mem_data_valid;
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    sensitive << i_resp_mem_data;
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    sensitive << r.state;
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    SC_METHOD(registers);
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    sensitive << i_clk.pos();
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    i0 = new ICache("i0");
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    i0->i_clk(i_clk);
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    i0->i_nrst(i_nrst);
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    i0->i_req_ctrl_valid(i_req_ctrl_valid);
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    i0->i_req_ctrl_addr(i_req_ctrl_addr);
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    i0->o_req_ctrl_ready(o_req_ctrl_ready);
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    i0->o_resp_ctrl_valid(o_resp_ctrl_valid);
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    i0->o_resp_ctrl_addr(o_resp_ctrl_addr);
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    i0->o_resp_ctrl_data(o_resp_ctrl_data);
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    i0->i_resp_ctrl_ready(i_resp_ctrl_ready);
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    i0->i_req_mem_ready(w_ctrl_req_ready);
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    i0->o_req_mem_valid(i.req_mem_valid);
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    i0->o_req_mem_write(i.req_mem_write);
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    i0->o_req_mem_addr(i.req_mem_addr);
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    i0->o_req_mem_strob(i.req_mem_strob);
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    i0->o_req_mem_data(i.req_mem_wdata);
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    i0->i_resp_mem_data_valid(w_ctrl_resp_mem_data_valid);
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    i0->i_resp_mem_data(wb_ctrl_resp_mem_data);
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    i0->o_istate(o_istate);
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    d0 = new DCache("d0");
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    d0->i_clk(i_clk);
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    d0->i_nrst(i_nrst);
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    d0->i_req_data_valid(i_req_data_valid);
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    d0->i_req_data_write(i_req_data_write);
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    d0->i_req_data_sz(i_req_data_size);
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    d0->i_req_data_addr(i_req_data_addr);
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    d0->i_req_data_data(i_req_data_data);
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    d0->o_req_data_ready(o_req_data_ready);
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    d0->o_resp_data_valid(o_resp_data_valid);
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    d0->o_resp_data_addr(o_resp_data_addr);
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    d0->o_resp_data_data(o_resp_data_data);
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    d0->i_resp_data_ready(i_resp_data_ready);
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    d0->i_req_mem_ready(w_data_req_ready);
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    d0->o_req_mem_valid(d.req_mem_valid);
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    d0->o_req_mem_write(d.req_mem_write);
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    d0->o_req_mem_addr(d.req_mem_addr);
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    d0->o_req_mem_strob(d.req_mem_strob);
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    d0->o_req_mem_data(d.req_mem_wdata);
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    d0->i_resp_mem_data_valid(w_data_resp_mem_data_valid);
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    d0->i_resp_mem_data(wb_data_resp_mem_data);
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    d0->o_dstate(o_dstate);
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#ifdef DBG_ICACHE_TB
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    i0_tb = new ICache_tb("ictb0");
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#endif
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};
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void CacheTop::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
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    if (o_vcd) {
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        sc_trace(o_vcd, i_req_data_valid, "/top/cache0/i_req_data_valid");
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        sc_trace(o_vcd, i_req_data_write, "/top/cache0/i_req_data_write");
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        sc_trace(o_vcd, i_req_data_addr, "/top/cache0/i_req_data_addr");
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        sc_trace(o_vcd, i_req_data_data, "/top/cache0/i_req_data_data");
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        sc_trace(o_vcd, w_data_resp_mem_data_valid, "/top/cache0/w_data_resp_mem_data_valid");
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        sc_trace(o_vcd, wb_data_resp_mem_data, "/top/cache0/wb_data_resp_mem_data");
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        sc_trace(o_vcd, w_ctrl_resp_mem_data_valid, "/top/cache0/w_ctrl_resp_mem_data_valid");
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        sc_trace(o_vcd, wb_ctrl_resp_mem_data, "/top/cache0/wb_ctrl_resp_mem_data");
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        sc_trace(o_vcd, i_req_mem_ready, "/top/cache0/i_req_mem_ready");
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        sc_trace(o_vcd, o_req_mem_valid, "/top/cache0/o_req_mem_valid");
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        sc_trace(o_vcd, o_req_mem_write, "/top/cache0/o_req_mem_write");
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        sc_trace(o_vcd, o_req_mem_addr, "/top/cache0/o_req_mem_addr");
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        sc_trace(o_vcd, o_req_mem_strob, "/top/cache0/o_req_mem_strob");
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        sc_trace(o_vcd, o_req_mem_data, "/top/cache0/o_req_mem_data");
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        sc_trace(o_vcd, i_resp_mem_data_valid, "/top/cache0/i_resp_mem_data_valid");
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        sc_trace(o_vcd, i_resp_mem_data, "/top/cache0/i_resp_mem_data");
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        sc_trace(o_vcd, o_istate, "/top/cache0/o_istate");
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        sc_trace(o_vcd, o_dstate, "/top/cache0/o_dstate");
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        sc_trace(o_vcd, o_cstate, "/top/cache0/o_cstate");
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    }
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    i0->generateVCD(i_vcd, o_vcd);
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    d0->generateVCD(i_vcd, o_vcd);
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}
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CacheTop::~CacheTop() {
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    delete i0;
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    delete d0;
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}
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void CacheTop::comb() {
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    bool w_mem_write;
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    sc_uint<BUS_ADDR_WIDTH> wb_mem_addr;
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    sc_uint<BUS_DATA_BYTES> wb_mem_strob;
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    sc_uint<BUS_DATA_WIDTH> wb_mem_wdata;
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    v = r;
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    w_mem_write = 0;
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    wb_mem_addr = 0;
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    wb_mem_strob = 0;
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    wb_mem_wdata = 0;
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    w_data_req_ready = 0;
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    w_data_resp_mem_data_valid = 0;
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    wb_data_resp_mem_data = 0;
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    w_ctrl_req_ready = 0;
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    w_ctrl_resp_mem_data_valid = 0;
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    wb_ctrl_resp_mem_data = 0;
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    switch (r.state.read()) {
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    case State_Idle:
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        if (d.req_mem_valid.read()) {
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            w_data_req_ready = i_req_mem_ready;
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            w_mem_write = d.req_mem_write;
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            wb_mem_addr = d.req_mem_addr;
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            wb_mem_strob = d.req_mem_strob;
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            wb_mem_wdata = d.req_mem_wdata;
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            if (i_req_mem_ready.read()) {
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                v.state = State_DMem;
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            }
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        } else if (i.req_mem_valid.read()) {
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            w_ctrl_req_ready = i_req_mem_ready;
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            w_mem_write = i.req_mem_write;
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            wb_mem_addr = i.req_mem_addr;
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            wb_mem_strob = i.req_mem_strob;
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            wb_mem_wdata = i.req_mem_wdata;
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            if (i_req_mem_ready.read()) {
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                v.state = State_IMem;
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            }
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        }
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        break;
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    case State_DMem:
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        w_data_req_ready = i_req_mem_ready;
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        w_mem_write = d.req_mem_write;
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        wb_mem_addr = d.req_mem_addr;
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        wb_mem_strob = d.req_mem_strob;
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        wb_mem_wdata = d.req_mem_wdata;
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        if (i_resp_mem_data_valid.read()) {
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            if (!d.req_mem_valid.read() && i.req_mem_valid.read()) {
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                v.state = State_IMem;
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                w_data_req_ready = 0;
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                w_ctrl_req_ready = i_req_mem_ready;
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                w_mem_write = i.req_mem_write;
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                wb_mem_addr = i.req_mem_addr;
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                wb_mem_strob = i.req_mem_strob;
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                wb_mem_wdata = i.req_mem_wdata;
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            } else if (!(d.req_mem_valid | i.req_mem_valid)) {
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                v.state = State_Idle;
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            }
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        }
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        w_data_resp_mem_data_valid = i_resp_mem_data_valid;
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        wb_data_resp_mem_data = i_resp_mem_data;
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        break;
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    case State_IMem:
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        w_ctrl_req_ready = i_req_mem_ready;
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        w_mem_write = i.req_mem_write;
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        wb_mem_addr = i.req_mem_addr;
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        wb_mem_strob = i.req_mem_strob;
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        wb_mem_wdata = i.req_mem_wdata;
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        if (i_resp_mem_data_valid.read()) {
188 
            if (d.req_mem_valid.read()) {
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                v.state = State_DMem;
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                w_data_req_ready = i_req_mem_ready;
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                w_ctrl_req_ready = 0;
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                w_mem_write = d.req_mem_write;
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                wb_mem_addr = d.req_mem_addr;
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                wb_mem_strob = d.req_mem_strob;
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                wb_mem_wdata = d.req_mem_wdata;
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            } else if (!(d.req_mem_valid | i.req_mem_valid)) {
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                v.state = State_Idle;
198 
            }
199 
        }
200 
        w_ctrl_resp_mem_data_valid = i_resp_mem_data_valid;
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        wb_ctrl_resp_mem_data = i_resp_mem_data;
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        break;
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    default:;
204 
    }
205 
 
206 
    if (!i_nrst.read()) {
207 
        v.state = State_Idle;
208 
    }
209 
 
210 
    o_req_mem_valid = i.req_mem_valid | d.req_mem_valid;
211 
    o_req_mem_write = w_mem_write;
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    o_req_mem_addr = wb_mem_addr;
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    o_req_mem_strob = wb_mem_strob;
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    o_req_mem_data = wb_mem_wdata;
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    o_cstate = r.state;
216 
}
217 
 
218 
void CacheTop::registers() {
219 
    r = v;
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}
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222 
}  // namespace debugger
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