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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [cache/] [dcache.cpp] - Blame information for rev 2

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1 2 sergeykhbr 
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      Data Cache.
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 */
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#include "dcache.h"
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namespace debugger {
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DCache::DCache(sc_module_name name_) : sc_module(name_) {
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    SC_METHOD(comb);
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    sensitive << i_nrst;
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    sensitive << i_req_data_valid;
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    sensitive << i_req_data_write;
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    sensitive << i_req_data_sz;
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    sensitive << i_req_data_addr;
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    sensitive << i_req_data_data;
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    sensitive << i_resp_mem_data_valid;
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    sensitive << i_resp_mem_data;
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    sensitive << i_req_mem_ready;
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    sensitive << i_resp_data_ready;
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    sensitive << r.dline_data;
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    sensitive << r.dline_addr_req;
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    sensitive << r.dline_size_req;
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    sensitive << r.state;
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    SC_METHOD(registers);
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    sensitive << i_clk.pos();
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};
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void DCache::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
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    if (o_vcd) {
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        sc_trace(o_vcd, i_req_data_valid, "/top/cache0/d0/i_req_data_valid");
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        sc_trace(o_vcd, i_req_data_write, "/top/cache0/d0/i_req_data_write");
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        sc_trace(o_vcd, i_req_data_sz, "/top/cache0/d0/i_req_data_sz");
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        sc_trace(o_vcd, i_req_data_addr, "/top/cache0/d0/i_req_data_addr");
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        sc_trace(o_vcd, i_req_data_data, "/top/cache0/d0/i_req_data_data");
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        sc_trace(o_vcd, o_req_mem_addr, "/top/cache0/d0/o_req_mem_addr");
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        sc_trace(o_vcd, o_req_mem_strob, "/top/cache0/d0/o_req_mem_strob");
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        sc_trace(o_vcd, o_req_mem_data, "/top/cache0/d0/o_req_mem_data");
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        sc_trace(o_vcd, o_resp_data_valid, "/top/cache0/d0/o_resp_data_valid");
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        sc_trace(o_vcd, o_resp_data_addr, "/top/cache0/d0/o_resp_data_addr");
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        sc_trace(o_vcd, o_resp_data_data, "/top/cache0/d0/o_resp_data_data");
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        sc_trace(o_vcd, r.dline_data, "/top/cache0/d0/r_dline_data");
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        sc_trace(o_vcd, r.dline_addr_req, "/top/cache0/d0/r_dline_addr_req");
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        sc_trace(o_vcd, r.dline_size_req, "/top/cache0/d0/r_dline_size_req");
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        sc_trace(o_vcd, r.state, "/top/cache0/d0/r_state");
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    }
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}
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53 
void DCache::comb() {
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    bool w_o_req_data_ready;
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    bool w_o_req_mem_valid;
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    sc_uint<BUS_ADDR_WIDTH> wb_o_req_mem_addr;
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    sc_uint<BUS_DATA_BYTES> wb_o_req_strob;
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    sc_uint<BUS_DATA_WIDTH> wb_o_req_wdata;
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    bool w_req_fire;
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    bool w_o_resp_valid;
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    sc_uint<BUS_ADDR_WIDTH> wb_o_resp_addr;
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    sc_uint<BUS_DATA_WIDTH> wb_resp_data_mux;
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    sc_uint<BUS_DATA_WIDTH> wb_o_resp_data;
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    sc_uint<BUS_DATA_WIDTH> wb_rtmp;
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66 
    v = r;
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68 
    wb_o_req_strob = 0;
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    wb_o_req_wdata = 0;
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    wb_o_resp_data = 0;
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    wb_rtmp = 0;
72 
 
73 
    switch (i_req_data_sz.read()) {
74 
    case 0:
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        wb_o_req_wdata = (i_req_data_data.read()(7, 0),
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            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
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            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
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            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
79 
            i_req_data_data.read()(7, 0));
80 
        if (i_req_data_addr.read()(2, 0) == 0x0) {
81 
            wb_o_req_strob = 0x01;
82 
        } else if (i_req_data_addr.read()(2, 0) == 0x1) {
83 
            wb_o_req_strob = 0x02;
84 
        } else if (i_req_data_addr.read()(2, 0) == 0x2) {
85 
            wb_o_req_strob = 0x04;
86 
        } else if (i_req_data_addr.read()(2, 0) == 0x3) {
87 
            wb_o_req_strob = 0x08;
88 
        } else if (i_req_data_addr.read()(2, 0) == 0x4) {
89 
            wb_o_req_strob = 0x10;
90 
        } else if (i_req_data_addr.read()(2, 0) == 0x5) {
91 
            wb_o_req_strob = 0x20;
92 
        } else if (i_req_data_addr.read()(2, 0) == 0x6) {
93 
            wb_o_req_strob = 0x40;
94 
        } else if (i_req_data_addr.read()(2, 0) == 0x7) {
95 
            wb_o_req_strob = 0x80;
96 
        }
97 
        break;
98 
    case 1:
99 
        wb_o_req_wdata = (i_req_data_data.read()(15, 0),
100 
            i_req_data_data.read()(15, 0), i_req_data_data.read()(15, 0),
101 
            i_req_data_data.read()(15, 0));
102 
        if (i_req_data_addr.read()(2, 1) == 0) {
103 
            wb_o_req_strob = 0x03;
104 
        } else if (i_req_data_addr.read()(2, 1) == 1) {
105 
            wb_o_req_strob = 0x0C;
106 
        } else if (i_req_data_addr.read()(2, 1) == 2) {
107 
            wb_o_req_strob = 0x30;
108 
        } else {
109 
            wb_o_req_strob = 0xC0;
110 
        }
111 
        break;
112 
    case 2:
113 
        wb_o_req_wdata = (i_req_data_data.read()(31, 0),
114 
                    i_req_data_data.read()(31, 0));
115 
        if (i_req_data_addr.read()[2]) {
116 
            wb_o_req_strob = 0xF0;
117 
        } else {
118 
            wb_o_req_strob = 0x0F;
119 
        }
120 
        break;
121 
    case 3:
122 
        wb_o_req_wdata = i_req_data_data;
123 
        wb_o_req_strob = 0xFF;
124 
        break;
125 
    default:;
126 
    }
127 
 
128 
    w_o_req_mem_valid = i_req_data_valid.read();
129 
    wb_o_req_mem_addr = i_req_data_addr.read()(BUS_ADDR_WIDTH-1, 3) << 3;
130 
    w_o_req_data_ready = i_req_mem_ready.read();
131 
    w_req_fire = i_req_data_valid.read() && w_o_req_data_ready;
132 
    switch (r.state.read()) {
133 
    case State_Idle:
134 
        if (i_req_data_valid.read()) {
135 
            if (i_req_mem_ready.read()) {
136 
                v.state = State_WaitResp;
137 
            } else {
138 
                v.state = State_WaitGrant;
139 
            }
140 
        }
141 
        break;
142 
    case State_WaitGrant:
143 
        if (i_req_mem_ready.read()) {
144 
            v.state = State_WaitResp;
145 
        }
146 
        break;
147 
    case State_WaitResp:
148 
        if (i_resp_mem_data_valid.read()) {
149 
            if (!i_resp_data_ready.read()) {
150 
                v.state = State_WaitAccept;
151 
            } else if (!i_req_data_valid.read()) {
152 
                v.state = State_Idle;
153 
            } else {
154 
                // New request
155 
                if (i_req_mem_ready.read()) {
156 
                    v.state = State_WaitResp;
157 
                } else {
158 
                    v.state = State_WaitGrant;
159 
                }
160 
            }
161 
        }
162 
        break;
163 
    case State_WaitAccept:
164 
        if (i_resp_data_ready.read()) {
165 
            if (!i_req_data_valid.read()) {
166 
                v.state = State_Idle;
167 
            } else {
168 
                if (i_req_mem_ready.read()) {
169 
                    v.state = State_WaitResp;
170 
                } else {
171 
                    v.state = State_WaitGrant;
172 
                }
173 
            }
174 
        }
175 
        break;
176 
    default:;
177 
    }
178 
 
179 
    if (w_req_fire) {
180 
        v.dline_addr_req = i_req_data_addr;
181 
        v.dline_size_req = i_req_data_sz;
182 
    }
183 
    if (i_resp_mem_data_valid.read()) {
184 
        v.dline_data =  i_resp_mem_data;
185 
    }
186 
 
187 
    wb_o_resp_addr = r.dline_addr_req;
188 
    if (r.state.read() == State_WaitAccept) {
189 
        w_o_resp_valid = 1;
190 
        wb_resp_data_mux = r.dline_data;
191 
    } else {
192 
        w_o_resp_valid = i_resp_mem_data_valid;
193 
        wb_resp_data_mux = i_resp_mem_data;
194 
    }
195 
 
196 
    switch (r.dline_addr_req.read()(2, 0)) {
197 
    case 1:
198 
        wb_rtmp = wb_resp_data_mux(63, 8);
199 
        break;
200 
    case 2:
201 
        wb_rtmp = wb_resp_data_mux(63, 16);
202 
        break;
203 
    case 3:
204 
        wb_rtmp = wb_resp_data_mux(63, 24);
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        break;
206 
    case 4:
207 
        wb_rtmp = wb_resp_data_mux(63, 32);
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        break;
209 
    case 5:
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        wb_rtmp = wb_resp_data_mux(63, 40);
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        break;
212 
    case 6:
213 
        wb_rtmp = wb_resp_data_mux(63, 48);
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        break;
215 
    case 7:
216 
        wb_rtmp = wb_resp_data_mux(63, 56);
217 
        break;
218 
    default:
219 
        wb_rtmp = wb_resp_data_mux;
220 
    }
221 
 
222 
    switch (r.dline_size_req.read()) {
223 
    case 0:
224 
        wb_o_resp_data = wb_rtmp(7, 0);
225 
        break;
226 
    case 1:
227 
        wb_o_resp_data = wb_rtmp(15, 0);
228 
        break;
229 
    case 2:
230 
        wb_o_resp_data = wb_rtmp(31, 0);
231 
        break;
232 
    default:
233 
        wb_o_resp_data = wb_rtmp;
234 
    }
235 
 
236 
    if (!i_nrst.read()) {
237 
        v.dline_addr_req = 0;
238 
        v.dline_size_req = 0;
239 
        v.dline_data = 0;
240 
        v.state = State_Idle;
241 
    }
242 
 
243 
    o_req_data_ready = w_o_req_data_ready;
244 
 
245 
    o_req_mem_valid = w_o_req_mem_valid;
246 
    o_req_mem_addr = wb_o_req_mem_addr;
247 
    o_req_mem_write = i_req_data_write;
248 
    o_req_mem_strob = wb_o_req_strob;
249 
    o_req_mem_data = wb_o_req_wdata;
250 
 
251 
    o_resp_data_valid = w_o_resp_valid;
252 
    o_resp_data_data = wb_o_resp_data;
253 
    o_resp_data_addr = wb_o_resp_addr;
254 
    o_dstate = r.state;
255 
}
256 
 
257 
void DCache::registers() {
258 
    r = v;
259 
}
260 
 
261 
}  // namespace debugger
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