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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief Instruction Cache.
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*/
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#ifndef __DEBUGGER_RIVERLIB_ICACHE_H__
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#define __DEBUGGER_RIVERLIB_ICACHE_H__
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#include <systemc.h>
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#include "../river_cfg.h"
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namespace debugger {
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//#define DBG_ICACHE_TB
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SC_MODULE(ICache) {
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sc_in<bool> i_clk;
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sc_in<bool> i_nrst;
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// Control path:
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sc_in<bool> i_req_ctrl_valid;
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_req_ctrl_addr;
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sc_out<bool> o_req_ctrl_ready;
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sc_out<bool> o_resp_ctrl_valid;
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_resp_ctrl_addr;
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sc_out<sc_uint<32>> o_resp_ctrl_data;
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sc_in<bool> i_resp_ctrl_ready;
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// Memory interface:
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sc_in<bool> i_req_mem_ready;
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sc_out<bool> o_req_mem_valid;
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sc_out<bool> o_req_mem_write;
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_req_mem_addr;
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sc_out<sc_uint<BUS_DATA_BYTES>> o_req_mem_strob;
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sc_out<sc_uint<BUS_DATA_WIDTH>> o_req_mem_data;
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sc_in<bool> i_resp_mem_data_valid;
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sc_in<sc_uint<BUS_DATA_WIDTH>> i_resp_mem_data;
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sc_out<sc_uint<2>> o_istate;
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void comb();
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void registers();
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SC_HAS_PROCESS(ICache);
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ICache(sc_module_name name_);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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enum EState {
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State_Idle,
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State_WaitGrant,
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State_WaitResp,
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State_WaitAccept
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};
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struct RegistersType {
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sc_signal<sc_uint<BUS_ADDR_WIDTH - 3>> iline_addr;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> iline_data;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> iline_addr_req;
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sc_signal<sc_uint<32>> iline_data_hit;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> iline_addr_hit;
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sc_signal<sc_uint<2>> state;
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sc_signal<bool> hit_line;
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} v, r;
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bool w_hit_req;
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bool w_hit_line;
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bool w_hit;
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};
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#ifdef DBG_ICACHE_TB
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SC_MODULE(ICache_tb) {
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void comb0();
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void registers() {
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r = v;
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}
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SC_HAS_PROCESS(ICache_tb);
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ICache_tb(sc_module_name name_) : sc_module(name_),
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w_clk("clk0", 10, SC_NS) {
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SC_METHOD(comb0);
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sensitive << w_nrst;
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sensitive << w_req_ctrl_valid;
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sensitive << wb_req_ctrl_addr;
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sensitive << w_req_ctrl_ready;
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sensitive << w_resp_ctrl_valid;
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sensitive << wb_resp_ctrl_addr;
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sensitive << wb_resp_ctrl_data;
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sensitive << w_resp_ctrl_ready;
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sensitive << w_req_mem_ready;
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sensitive << w_req_mem_valid;
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sensitive << w_req_mem_write;
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sensitive << wb_req_mem_addr;
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sensitive << wb_req_mem_strob;
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sensitive << wb_req_mem_data;
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sensitive << w_resp_mem_data_valid;
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sensitive << wb_resp_mem_data;
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sensitive << wb_istate;
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sensitive << r.clk_cnt;
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sensitive << r.mem_raddr;
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sensitive << r.mem_state;
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sensitive << r.mem_cnt;
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sensitive << r.mem_wait_cnt;
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sensitive << r.fetch_state;
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sensitive << r.fetch_cnt;
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SC_METHOD(registers);
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sensitive << w_clk.posedge_event();
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tt = new ICache("tt");
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tt->i_clk(w_clk);
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tt->i_nrst(w_nrst);
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tt->i_req_ctrl_valid(w_req_ctrl_valid);
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tt->i_req_ctrl_addr(wb_req_ctrl_addr);
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tt->o_req_ctrl_ready(w_req_ctrl_ready);
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tt->o_resp_ctrl_valid(w_resp_ctrl_valid);
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tt->o_resp_ctrl_addr(wb_resp_ctrl_addr);
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tt->o_resp_ctrl_data(wb_resp_ctrl_data);
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tt->i_resp_ctrl_ready(w_resp_ctrl_ready);
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tt->i_req_mem_ready(w_req_mem_ready);
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tt->o_req_mem_valid(w_req_mem_valid);
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tt->o_req_mem_write(w_req_mem_write);
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tt->o_req_mem_addr(wb_req_mem_addr);
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tt->o_req_mem_strob(wb_req_mem_strob);
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tt->o_req_mem_data(wb_req_mem_data);
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tt->i_resp_mem_data_valid(w_resp_mem_data_valid);
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tt->i_resp_mem_data(wb_resp_mem_data);
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tt->o_istate(wb_istate);
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tb_vcd = sc_create_vcd_trace_file("icache_tb");
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tb_vcd->set_time_unit(1, SC_PS);
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sc_trace(tb_vcd, w_nrst, "w_nrst");
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sc_trace(tb_vcd, w_clk, "w_clk");
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sc_trace(tb_vcd, r.clk_cnt, "clk_cnt");
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sc_trace(tb_vcd, w_req_ctrl_valid, "w_req_ctrl_valid");
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sc_trace(tb_vcd, wb_req_ctrl_addr, "wb_req_ctrl_addr");
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sc_trace(tb_vcd, w_req_ctrl_ready, "w_req_ctrl_ready");
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sc_trace(tb_vcd, w_resp_ctrl_valid, "w_resp_ctrl_valid");
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sc_trace(tb_vcd, wb_resp_ctrl_addr, "wb_resp_ctrl_addr");
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sc_trace(tb_vcd, wb_resp_ctrl_data, "wb_resp_ctrl_data");
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sc_trace(tb_vcd, w_resp_ctrl_ready, "w_resp_ctrl_ready");
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sc_trace(tb_vcd, w_req_mem_ready, "w_req_mem_ready");
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sc_trace(tb_vcd, w_req_mem_valid, "w_req_mem_valid");
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sc_trace(tb_vcd, w_req_mem_write, "w_req_mem_write");
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sc_trace(tb_vcd, wb_req_mem_addr, "wb_req_mem_addr");
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sc_trace(tb_vcd, wb_req_mem_strob, "wb_req_mem_strob");
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sc_trace(tb_vcd, wb_req_mem_data, "wb_req_mem_data");
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sc_trace(tb_vcd, w_resp_mem_data_valid, "w_resp_mem_data_valid");
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sc_trace(tb_vcd, wb_resp_mem_data, "wb_resp_mem_data");
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sc_trace(tb_vcd, wb_istate, "wb_istate");
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sc_trace(tb_vcd, wb_istate_z, "wb_istate_z");
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sc_trace(tb_vcd, w_ierr_state, "w_ierr_state");
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sc_trace(tb_vcd, r.mem_state, "r_mem_state");
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sc_trace(tb_vcd, r.mem_raddr, "r_mem_raddr");
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tt->generateVCD(tb_vcd, tb_vcd);
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}
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private:
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ICache *tt;
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sc_clock w_clk;
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sc_signal<bool> w_nrst;
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// Control path:
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sc_signal<bool> w_req_ctrl_valid;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_req_ctrl_addr;
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sc_signal<bool> w_req_ctrl_ready;
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sc_signal<bool> w_resp_ctrl_valid;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_resp_ctrl_addr;
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sc_signal<sc_uint<32>> wb_resp_ctrl_data;
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sc_signal<bool> w_resp_ctrl_ready;
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// Memory interface:
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sc_signal<bool> w_req_mem_ready;
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sc_signal<bool> w_req_mem_valid;
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sc_signal<bool> w_req_mem_write;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_req_mem_addr;
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sc_signal<sc_uint<BUS_DATA_BYTES>> wb_req_mem_strob;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_req_mem_data;
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sc_signal<bool> w_resp_mem_data_valid;
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sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_resp_mem_data;
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sc_signal<sc_uint<2>> wb_istate;
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struct RegistersType {
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sc_signal<sc_uint<32>> clk_cnt;
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sc_signal<sc_uint<2>> fetch_state;
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sc_signal<sc_uint<8>> fetch_cnt;
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sc_signal<sc_uint<8>> fetch_wait_cnt;
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sc_signal<sc_uint<2>> mem_state;
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sc_signal<sc_uint<32>> mem_raddr;
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sc_signal<sc_uint<8>> mem_cnt;
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sc_signal<sc_uint<8>> mem_wait_cnt;
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} v, r;
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sc_trace_file *tb_vcd;
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};
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#endif // DBG_ICACHE_TB
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_ICACHE_H__
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