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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [decoder.cpp] - Blame information for rev 2

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1 2 sergeykhbr 
/**
2 
 * @file
3 
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4 
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5 
 * @brief      CPU Instruction Decoder stage.
6 
 */
7 
 
8 
#include "decoder.h"
9 
 
10 
namespace debugger {
11 
 
12 
InstrDecoder::InstrDecoder(sc_module_name name_) : sc_module(name_) {
13 
    SC_METHOD(comb);
14 
    sensitive << i_nrst;
15 
    sensitive << i_any_hold;
16 
    sensitive << i_f_valid;
17 
    sensitive << i_f_pc;
18 
    sensitive << i_f_instr;
19 
    sensitive << r.valid;
20 
    sensitive << r.pc;
21 
    sensitive << r.instr;
22 
    sensitive << r.memop_load;
23 
    sensitive << r.memop_store;
24 
 
25 
    SC_METHOD(registers);
26 
    sensitive << i_clk.pos();
27 
};
28 
 
29 
void InstrDecoder::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
30 
    if (o_vcd) {
31 
        sc_trace(o_vcd, i_any_hold, "/top/proc0/dec0/i_any_hold");
32 
        sc_trace(o_vcd, o_valid, "/top/proc0/dec0/o_valid");
33 
        sc_trace(o_vcd, o_pc, "/top/proc0/dec0/o_pc");
34 
        sc_trace(o_vcd, o_instr, "/top/proc0/dec0/o_instr");
35 
        sc_trace(o_vcd, o_isa_type, "/top/proc0/dec0/o_isa_type");
36 
        sc_trace(o_vcd, o_instr_vec, "/top/proc0/dec0/o_instr_vec");
37 
        sc_trace(o_vcd, o_exception, "/top/proc0/dec0/o_exception");
38 
    }
39 
}
40 
 
41 
void InstrDecoder::comb() {
42 
    v = r;
43 
 
44 
    bool w_o_valid;
45 
    bool w_error = false;
46 
    sc_uint<32> wb_instr = i_f_instr.read();
47 
    sc_uint<5> wb_opcode1 = wb_instr(6, 2);
48 
    sc_uint<3> wb_opcode2 = wb_instr(14, 12);
49 
    sc_bv<Instr_Total> wb_dec = 0;
50 
    sc_bv<ISA_Total> wb_isa_type = 0;
51 
 
52 
    if (wb_instr(1, 0) != 0x3) {
53 
        w_error = true;
54 
    }
55 
 
56 
    switch (wb_opcode1) {
57 
    case OPCODE_ADD:
58 
        wb_isa_type[ISA_R_type] = 1;
59 
        switch (wb_opcode2) {
60 
        case 0:
61 
            if (wb_instr(31, 25) == 0x00) {
62 
                wb_dec[Instr_ADD] = 1;
63 
            } else if (wb_instr(31, 25) == 0x01) {
64 
                wb_dec[Instr_MUL] = 1;
65 
            } else if (wb_instr(31, 25) == 0x20) {
66 
                wb_dec[Instr_SUB] = 1;
67 
            } else {
68 
                w_error = true;
69 
            }
70 
            break;
71 
        case 0x1:
72 
            wb_dec[Instr_SLL] = 1;
73 
            break;
74 
        case 0x2:
75 
            wb_dec[Instr_SLT] = 1;
76 
            break;
77 
        case 0x3:
78 
            wb_dec[Instr_SLTU] = 1;
79 
            break;
80 
        case 0x4:
81 
            if (wb_instr(31, 25) == 0x00) {
82 
                wb_dec[Instr_XOR] = 1;
83 
            } else if (wb_instr(31, 25) == 0x01) {
84 
                wb_dec[Instr_DIV] = 1;
85 
            } else {
86 
                w_error = true;
87 
            }
88 
            break;
89 
        case 0x5:
90 
            if (wb_instr(31, 25) == 0x00) {
91 
                wb_dec[Instr_SRL] = 1;
92 
            } else if (wb_instr(31, 25) == 0x01) {
93 
                wb_dec[Instr_DIVU] = 1;
94 
            } else if (wb_instr(31, 25) == 0x20) {
95 
                wb_dec[Instr_SRA] = 1;
96 
            } else {
97 
                w_error = true;
98 
            }
99 
            break;
100 
        case 0x6:
101 
            if (wb_instr(31, 25) == 0x00) {
102 
                wb_dec[Instr_OR] = 1;
103 
            } else if (wb_instr(31, 25) == 0x01) {
104 
                wb_dec[Instr_REM] = 1;
105 
            } else {
106 
                w_error = true;
107 
            }
108 
            break;
109 
        case 0x7:
110 
            if (wb_instr(31, 25) == 0x00) {
111 
                wb_dec[Instr_AND] = 1;
112 
            } else if (wb_instr(31, 25) == 0x01) {
113 
                wb_dec[Instr_REMU] = 1;
114 
            } else {
115 
                w_error = true;
116 
            }
117 
            break;
118 
        default:
119 
            w_error = true;
120 
        }
121 
        break;
122 
    case OPCODE_ADDI:
123 
        wb_isa_type[ISA_I_type] = 1;
124 
        switch (wb_opcode2) {
125 
        case 0:
126 
            wb_dec[Instr_ADDI] = 1;
127 
            break;
128 
        case 0x1:
129 
            wb_dec[Instr_SLLI] = 1;
130 
            break;
131 
        case 0x2:
132 
            wb_dec[Instr_SLTI] = 1;
133 
            break;
134 
        case 0x3:
135 
            wb_dec[Instr_SLTIU] = 1;
136 
            break;
137 
        case 0x4:
138 
            wb_dec[Instr_XORI] = 1;
139 
            break;
140 
        case 0x5:
141 
            if (wb_instr(31, 26) == 0x00) {
142 
                wb_dec[Instr_SRLI] = 1;
143 
            } else if (wb_instr(31, 26) == 0x10) {
144 
                wb_dec[Instr_SRAI] = 1;
145 
            } else {
146 
                w_error = true;
147 
            }
148 
            break;
149 
        case 0x6:
150 
            wb_dec[Instr_ORI] = 1;
151 
            break;
152 
        case 7:
153 
            wb_dec[Instr_ANDI] = 1;
154 
            break;
155 
        default:
156 
            w_error = true;
157 
        }
158 
        break;
159 
    case OPCODE_ADDIW:
160 
        wb_isa_type[ISA_I_type] = 1;
161 
        switch (wb_opcode2) {
162 
        case 0:
163 
            wb_dec[Instr_ADDIW] = 1;
164 
            break;
165 
        case 0x1:
166 
            wb_dec[Instr_SLLIW] = 1;
167 
            break;
168 
        case 0x5:
169 
            if (wb_instr(31, 25) == 0x00) {
170 
                wb_dec[Instr_SRLIW] = 1;
171 
            } else if (wb_instr(31, 25) == 0x20) {
172 
                wb_dec[Instr_SRAIW] = 1;
173 
            } else {
174 
                w_error = true;
175 
            }
176 
            break;
177 
        default:
178 
            w_error = true;
179 
        }
180 
        break;
181 
    case OPCODE_ADDW:
182 
        wb_isa_type[ISA_R_type] = 1;
183 
        switch (wb_opcode2) {
184 
        case 0:
185 
            if (wb_instr(31, 25) == 0x00) {
186 
                wb_dec[Instr_ADDW] = 1;
187 
            } else if (wb_instr(31, 25) == 0x01) {
188 
                wb_dec[Instr_MULW] = 1;
189 
            } else if (wb_instr(31, 25) == 0x20) {
190 
                wb_dec[Instr_SUBW] = 1;
191 
            } else {
192 
                w_error = true;
193 
            }
194 
            break;
195 
        case 0x1:
196 
            wb_dec[Instr_SLLW] = 1;
197 
            break;
198 
        case 0x4:
199 
            if (wb_instr(31, 25) == 0x01) {
200 
                wb_dec[Instr_DIVW] = 1;
201 
            } else {
202 
                w_error = true;
203 
            }
204 
            break;
205 
        case 0x5:
206 
            if (wb_instr(31, 25) == 0x00) {
207 
                wb_dec[Instr_SRLW] = 1;
208 
            } else if (wb_instr(31, 25) == 0x01) {
209 
                wb_dec[Instr_DIVUW] = 1;
210 
            } else if (wb_instr(31, 25) == 0x20) {
211 
                wb_dec[Instr_SRAW] = 1;
212 
            } else {
213 
                w_error = true;
214 
            }
215 
            break;
216 
        case 0x6:
217 
            if (wb_instr(31, 25) == 0x01) {
218 
                wb_dec[Instr_REMW] = 1;
219 
            } else {
220 
                w_error = true;
221 
            }
222 
            break;
223 
        case 0x7:
224 
            if (wb_instr(31, 25) == 0x01) {
225 
                wb_dec[Instr_REMUW] = 1;
226 
            } else {
227 
                w_error = true;
228 
            }
229 
            break;
230 
        default:
231 
            w_error = true;
232 
        }
233 
        break;
234 
    case OPCODE_AUIPC:
235 
        wb_isa_type[ISA_U_type] = 1;
236 
        wb_dec[Instr_AUIPC] = 1;
237 
        break;
238 
    case OPCODE_BEQ:
239 
        wb_isa_type[ISA_SB_type] = 1;
240 
        switch (wb_opcode2) {
241 
        case 0:
242 
            wb_dec[Instr_BEQ] = 1;
243 
            break;
244 
        case 1:
245 
            wb_dec[Instr_BNE] = 1;
246 
            break;
247 
        case 4:
248 
            wb_dec[Instr_BLT] = 1;
249 
            break;
250 
        case 5:
251 
            wb_dec[Instr_BGE] = 1;
252 
            break;
253 
        case 6:
254 
            wb_dec[Instr_BLTU] = 1;
255 
            break;
256 
        case 7:
257 
            wb_dec[Instr_BGEU] = 1;
258 
            break;
259 
        default:
260 
            w_error = true;
261 
        }
262 
        break;
263 
    case OPCODE_JAL:
264 
        wb_isa_type[ISA_UJ_type] = 1;
265 
        wb_dec[Instr_JAL] = 1;
266 
        break;
267 
    case OPCODE_JALR:
268 
        wb_isa_type[ISA_I_type] = 1;
269 
        switch (wb_opcode2) {
270 
        case 0:
271 
            wb_dec[Instr_JALR] = 1;
272 
            break;
273 
        default:
274 
            w_error = true;
275 
        }
276 
        break;
277 
    case OPCODE_LB:
278 
        wb_isa_type[ISA_I_type] = 1;
279 
        switch (wb_opcode2) {
280 
        case 0:
281 
            wb_dec[Instr_LB] = 1;
282 
            break;
283 
        case 1:
284 
            wb_dec[Instr_LH] = 1;
285 
            break;
286 
        case 2:
287 
            wb_dec[Instr_LW] = 1;
288 
            break;
289 
        case 3:
290 
            wb_dec[Instr_LD] = 1;
291 
            break;
292 
        case 4:
293 
            wb_dec[Instr_LBU] = 1;
294 
            break;
295 
        case 5:
296 
            wb_dec[Instr_LHU] = 1;
297 
            break;
298 
        case 6:
299 
            wb_dec[Instr_LWU] = 1;
300 
            break;
301 
        default:
302 
            w_error = true;
303 
        }
304 
        break;
305 
    case OPCODE_LUI:
306 
        wb_isa_type[ISA_U_type] = 1;
307 
        wb_dec[Instr_LUI] = 1;
308 
        break;
309 
    case OPCODE_SB:
310 
        wb_isa_type[ISA_S_type] = 1;
311 
        switch (wb_opcode2) {
312 
        case 0:
313 
            wb_dec[Instr_SB] = 1;
314 
            break;
315 
        case 1:
316 
            wb_dec[Instr_SH] = 1;
317 
            break;
318 
        case 2:
319 
            wb_dec[Instr_SW] = 1;
320 
            break;
321 
        case 3:
322 
            wb_dec[Instr_SD] = 1;
323 
            break;
324 
        default:
325 
            w_error = true;
326 
        }
327 
        break;
328 
    case OPCODE_CSRR:
329 
        wb_isa_type[ISA_I_type] = 1;
330 
        switch (wb_opcode2) {
331 
        case 0:
332 
            if (wb_instr == 0x00000073) {
333 
                wb_dec[Instr_ECALL] = 1;
334 
            } else if (wb_instr == 0x00100073) {
335 
                wb_dec[Instr_EBREAK] = 1;
336 
            } else if (wb_instr == 0x00200073) {
337 
                wb_dec[Instr_URET] = 1;
338 
            } else if (wb_instr == 0x10200073) {
339 
                wb_dec[Instr_SRET] = 1;
340 
            } else if (wb_instr == 0x20200073) {
341 
                wb_dec[Instr_HRET] = 1;
342 
            } else if (wb_instr == 0x30200073) {
343 
                wb_dec[Instr_MRET] = 1;
344 
            } else {
345 
                w_error = true;
346 
            }
347 
            break;
348 
        case 1:
349 
            wb_dec[Instr_CSRRW] = 1;
350 
            break;
351 
        case 2:
352 
            wb_dec[Instr_CSRRS] = 1;
353 
            break;
354 
        case 3:
355 
            wb_dec[Instr_CSRRC] = 1;
356 
            break;
357 
        case 5:
358 
            wb_dec[Instr_CSRRWI] = 1;
359 
            break;
360 
        case 6:
361 
            wb_dec[Instr_CSRRSI] = 1;
362 
            break;
363 
        case 7:
364 
            wb_dec[Instr_CSRRCI] = 1;
365 
            break;
366 
        default:
367 
            w_error = true;
368 
        }
369 
        break;
370 
    case OPCODE_FENCE:
371 
        switch (wb_opcode2) {
372 
        case 0:
373 
            wb_dec[Instr_FENCE] = 1;
374 
            break;
375 
        case 1:
376 
            wb_dec[Instr_FENCE_I] = 1;
377 
            break;
378 
        default:
379 
            w_error = true;
380 
        }
381 
        break;
382 
 
383 
    default:
384 
        w_error = true;
385 
    }
386 
 
387 
 
388 
    if (i_f_valid.read()) {
389 
        v.valid = 1;
390 
        v.pc = i_f_pc;
391 
        v.instr = wb_instr;
392 
 
393 
        v.isa_type = wb_isa_type;
394 
        v.instr_vec = wb_dec;
395 
        v.memop_store = (wb_dec[Instr_SD] | wb_dec[Instr_SW]
396 
                | wb_dec[Instr_SH] | wb_dec[Instr_SB]).to_bool();
397 
        v.memop_load = (wb_dec[Instr_LD] | wb_dec[Instr_LW]
398 
                | wb_dec[Instr_LH] | wb_dec[Instr_LB]
399 
                | wb_dec[Instr_LWU] | wb_dec[Instr_LHU]
400 
                | wb_dec[Instr_LBU]).to_bool();
401 
        v.memop_sign_ext = (wb_dec[Instr_LD] | wb_dec[Instr_LW]
402 
                | wb_dec[Instr_LH] | wb_dec[Instr_LB]).to_bool();
403 
        if (wb_dec[Instr_LD] || wb_dec[Instr_SD]) {
404 
            v.memop_size = MEMOP_8B;
405 
        } else if (wb_dec[Instr_LW] || wb_dec[Instr_LWU] || wb_dec[Instr_SW]) {
406 
            v.memop_size = MEMOP_4B;
407 
        } else if (wb_dec[Instr_LH] || wb_dec[Instr_LHU] || wb_dec[Instr_SH]) {
408 
            v.memop_size = MEMOP_2B;
409 
        } else {
410 
            v.memop_size = MEMOP_1B;
411 
        }
412 
        v.unsigned_op = (wb_dec[Instr_DIVU] | wb_dec[Instr_REMU] |
413 
                wb_dec[Instr_DIVUW] | wb_dec[Instr_REMUW]).to_bool();
414 
 
415 
        v.rv32 = (wb_dec[Instr_ADDW] | wb_dec[Instr_ADDIW]
416 
            | wb_dec[Instr_SLLW] | wb_dec[Instr_SLLIW] | wb_dec[Instr_SRAW]
417 
            | wb_dec[Instr_SRAIW]
418 
            | wb_dec[Instr_SRLW] | wb_dec[Instr_SRLIW] | wb_dec[Instr_SUBW]
419 
            | wb_dec[Instr_DIVW] | wb_dec[Instr_DIVUW] | wb_dec[Instr_MULW]
420 
            | wb_dec[Instr_REMW] | wb_dec[Instr_REMUW]).to_bool();
421 
 
422 
        v.instr_unimplemented = w_error;
423 
    } else if (!i_any_hold.read()) {
424 
        v.valid = 0;
425 
    }
426 
    w_o_valid = r.valid.read() && !i_any_hold.read();
427 
 
428 
    if (!i_nrst.read()) {
429 
        v.valid = false;
430 
        v.pc = 0;
431 
        v.instr = 0;
432 
        v.isa_type = 0;
433 
        v.instr_vec = 0;
434 
        v.memop_store = 0;
435 
        v.memop_load = 0;
436 
        v.memop_sign_ext = 0;
437 
        v.memop_size = MEMOP_1B;
438 
        v.unsigned_op = 0;
439 
        v.rv32 = 0;
440 
 
441 
        v.instr_unimplemented = !wb_dec.or_reduce();
442 
    }
443 
 
444 
    o_valid = w_o_valid;
445 
    o_pc = r.pc;
446 
    o_instr = r.instr;
447 
    o_memop_load = r.memop_load;
448 
    o_memop_store = r.memop_store;
449 
    o_memop_sign_ext = r.memop_sign_ext;
450 
    o_memop_size = r.memop_size;
451 
    o_unsigned_op = r.unsigned_op;
452 
    o_rv32 = r.rv32;
453 
    o_isa_type = r.isa_type;
454 
    o_instr_vec = r.instr_vec;
455 
    o_exception = r.instr_unimplemented;
456 
}
457 
 
458 
void InstrDecoder::registers() {
459 
    r = v;
460 
}
461 
 
462 
}  // namespace debugger
463 
 

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