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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief CPU Instruction Decoder stage.
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*/
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#include "decoder.h"
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namespace debugger {
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InstrDecoder::InstrDecoder(sc_module_name name_) : sc_module(name_) {
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SC_METHOD(comb);
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sensitive << i_nrst;
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sensitive << i_any_hold;
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sensitive << i_f_valid;
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sensitive << i_f_pc;
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sensitive << i_f_instr;
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sensitive << r.valid;
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sensitive << r.pc;
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sensitive << r.instr;
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sensitive << r.memop_load;
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sensitive << r.memop_store;
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SC_METHOD(registers);
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sensitive << i_clk.pos();
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};
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void InstrDecoder::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
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if (o_vcd) {
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sc_trace(o_vcd, i_any_hold, "/top/proc0/dec0/i_any_hold");
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sc_trace(o_vcd, o_valid, "/top/proc0/dec0/o_valid");
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sc_trace(o_vcd, o_pc, "/top/proc0/dec0/o_pc");
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sc_trace(o_vcd, o_instr, "/top/proc0/dec0/o_instr");
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sc_trace(o_vcd, o_isa_type, "/top/proc0/dec0/o_isa_type");
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sc_trace(o_vcd, o_instr_vec, "/top/proc0/dec0/o_instr_vec");
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sc_trace(o_vcd, o_exception, "/top/proc0/dec0/o_exception");
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sc_trace(o_vcd, o_compressed, "/top/proc0/dec0/o_compressed");
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}
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}
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void InstrDecoder::comb() {
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v = r;
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bool w_o_valid;
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bool w_error = false;
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bool w_compressed = false;
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sc_uint<32> wb_instr = i_f_instr.read();
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sc_uint<32> wb_instr_out;
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sc_uint<5> wb_opcode1;
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sc_uint<3> wb_opcode2;
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sc_bv<Instr_Total> wb_dec = 0;
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sc_bv<ISA_Total> wb_isa_type = 0;
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if (wb_instr(1, 0) != 0x3) {
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w_compressed = 1;
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wb_opcode1 = (wb_instr(15, 13), wb_instr(1, 0));
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wb_instr_out = 0x00000003;
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switch (wb_opcode1) {
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case OPCODE_C_ADDI4SPN:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ADDI] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(4, 2); // rd
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wb_instr_out(19, 15) = 0x2; // rs1 = sp
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wb_instr_out(29, 22) =
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(wb_instr(10, 7), wb_instr(12, 11), wb_instr[5], wb_instr[6]);
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break;
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case OPCODE_C_NOP_ADDI:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ADDI] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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wb_instr_out(24, 20) = wb_instr(6, 2); // imm
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if (wb_instr[12]) {
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wb_instr_out(31, 25) = ~0;
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}
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break;
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case OPCODE_C_SLLI:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_SLLI] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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wb_instr_out(25, 20) = (wb_instr[12], wb_instr(6, 2)); // shamt
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break;
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case OPCODE_C_JAL_ADDIW:
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// JAL is the RV32C only instruction
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ADDIW] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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wb_instr_out(24, 20) = wb_instr(6, 2); // imm
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if (wb_instr[12]) {
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wb_instr_out(31, 25) = ~0;
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}
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break;
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case OPCODE_C_LW:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_LW] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(4, 2); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(26, 22) =
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(wb_instr[5], wb_instr(12, 10), wb_instr[6]);
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break;
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case OPCODE_C_LI: // ADDI rd = r0 + imm
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ADDI] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(24, 20) = wb_instr(6, 2); // imm
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if (wb_instr[12]) {
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wb_instr_out(31, 25) = ~0;
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}
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break;
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case OPCODE_C_LWSP:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_LW] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = 0x2; // rs1 = sp
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wb_instr_out(27, 22) =
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(wb_instr(3, 2), wb_instr[12], wb_instr(6, 4));
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break;
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case OPCODE_C_LD:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_LD] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(4, 2); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(27, 23) =
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(wb_instr[6], wb_instr[5], wb_instr(12, 10));
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break;
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case OPCODE_C_ADDI16SP_LUI:
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if (wb_instr(11, 7) == 0x2) {
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ADDI] = 1;
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wb_instr_out(11, 7) = 0x2; // rd = sp
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wb_instr_out(19, 15) = 0x2; // rs1 = sp
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wb_instr_out(28, 24) =
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(wb_instr(4, 3), wb_instr[5], wb_instr[2], wb_instr[6]);
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if (wb_instr[12]) {
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wb_instr_out(31, 29) = ~0;
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}
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} else {
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wb_isa_type[ISA_U_type] = 1;
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wb_dec[Instr_LUI] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(16, 12) = wb_instr(6, 2);
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if (wb_instr[12]) {
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wb_instr_out(31, 17) = ~0;
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}
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}
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break;
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case OPCODE_C_LDSP:
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_LD] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = 0x2; // rs1 = sp
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wb_instr_out(28, 23) =
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(wb_instr(4, 2), wb_instr[12], wb_instr(6, 5));
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break;
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case OPCODE_C_MATH:
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if (wb_instr(11, 10) == 0) {
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_SRLI] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(9, 7); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(25, 20) = (wb_instr[12], wb_instr(6, 2)); // shamt
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} else if (wb_instr(11, 10) == 1) {
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_SRAI] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(9, 7); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(25, 20) = (wb_instr[12], wb_instr(6, 2)); // shamt
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} else if (wb_instr(11, 10) == 2) {
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wb_isa_type[ISA_I_type] = 1;
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wb_dec[Instr_ANDI] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(9, 7); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(24, 20) = wb_instr(6, 2); // imm
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if (wb_instr[12]) {
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wb_instr_out(31, 25) = ~0;
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}
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} else if (wb_instr[12] == 0) {
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wb_isa_type[ISA_R_type] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(9, 7); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(24, 20) = 0x8 | wb_instr(4, 2); // rs2
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switch (wb_instr(6, 5)) {
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case 0:
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wb_dec[Instr_SUB] = 1;
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break;
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case 1:
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wb_dec[Instr_XOR] = 1;
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break;
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case 2:
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wb_dec[Instr_OR] = 1;
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break;
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default:
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wb_dec[Instr_AND] = 1;
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}
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} else {
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wb_isa_type[ISA_R_type] = 1;
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wb_instr_out(11, 7) = 0x8 | wb_instr(9, 7); // rd
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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wb_instr_out(24, 20) = 0x8 | wb_instr(4, 2); // rs2
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switch (wb_instr(6, 5)) {
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case 0:
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wb_dec[Instr_SUBW] = 1;
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break;
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case 1:
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wb_dec[Instr_ADDW] = 1;
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break;
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default:
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w_error = true;
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}
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}
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break;
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case OPCODE_C_JR_MV_EBREAK_JALR_ADD:
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wb_isa_type[ISA_I_type] = 1;
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if (wb_instr[12] == 0) {
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if (wb_instr(6, 2) == 0) {
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wb_dec[Instr_JALR] = 1;
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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} else {
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wb_dec[Instr_ADDI] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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wb_instr_out(19, 15) = wb_instr(6, 2); // rs1
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}
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} else {
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if (wb_instr(11, 7) == 0 && wb_instr(6, 2) == 0) {
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wb_dec[Instr_EBREAK] = 1;
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} else if (wb_instr(6, 2) == 0) {
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wb_dec[Instr_JALR] = 1;
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wb_instr_out(11, 7) = 0x1; // rd = ra
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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| 233 |
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} else {
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wb_dec[Instr_ADD] = 1;
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wb_isa_type[ISA_R_type] = 1;
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wb_instr_out(11, 7) = wb_instr(11, 7); // rd
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| 237 |
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wb_instr_out(19, 15) = wb_instr(11, 7); // rs1
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| 238 |
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wb_instr_out(24, 20) = wb_instr(6, 2); // rs2
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| 239 |
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}
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| 240 |
3 |
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}
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| 241 |
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break;
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| 242 |
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case OPCODE_C_J: // JAL with rd = 0
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wb_isa_type[ISA_UJ_type] = 1;
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wb_dec[Instr_JAL] = 1;
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| 245 |
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wb_instr_out[20] = wb_instr[12]; // imm11
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| 246 |
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wb_instr_out(23, 21) = wb_instr(5, 3); // imm10_1(3:1)
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| 247 |
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wb_instr_out[24] = wb_instr[11]; // imm10_1(4)
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| 248 |
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wb_instr_out[25] = wb_instr[2]; // imm10_1(5)
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| 249 |
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wb_instr_out[26] = wb_instr[7]; // imm10_1(6)
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| 250 |
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wb_instr_out[27] = wb_instr[6]; // imm10_1(7)
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| 251 |
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wb_instr_out(29, 28) = wb_instr(10, 9); // imm10_1(9:8)
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| 252 |
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wb_instr_out[30] = wb_instr[8]; // imm10_1(10)
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| 253 |
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if (wb_instr[12]) {
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wb_instr_out(19, 12) = ~0; // imm19_12
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| 255 |
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wb_instr_out[31] = 1; // imm20
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| 256 |
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}
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| 257 |
3 |
sergeykhbr |
break;
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| 258 |
4 |
sergeykhbr |
case OPCODE_C_SW:
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| 259 |
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wb_isa_type[ISA_S_type] = 1;
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| 260 |
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wb_dec[Instr_SW] = 1;
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| 261 |
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wb_instr_out(24, 20) = 0x8 | wb_instr(4, 2); // rs2
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| 262 |
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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| 263 |
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wb_instr_out(11, 9) = (wb_instr(11, 10), wb_instr[6]);
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| 264 |
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wb_instr_out(26, 25) = (wb_instr[5] , wb_instr[12]);
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| 265 |
3 |
sergeykhbr |
break;
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| 266 |
4 |
sergeykhbr |
case OPCODE_C_BEQZ:
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| 267 |
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wb_isa_type[ISA_SB_type] = 1;
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| 268 |
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wb_dec[Instr_BEQ] = 1;
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| 269 |
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wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
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| 270 |
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wb_instr_out(11, 8) = (wb_instr(11, 10), wb_instr(4, 3));
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| 271 |
|
|
wb_instr_out(27, 25) = (wb_instr(6, 5), wb_instr[2]);
|
| 272 |
|
|
if (wb_instr[12]) {
|
| 273 |
|
|
wb_instr_out(30, 28) = ~0;
|
| 274 |
|
|
wb_instr_out[7] = 1;
|
| 275 |
|
|
wb_instr_out[31] = 1;
|
| 276 |
|
|
}
|
| 277 |
3 |
sergeykhbr |
break;
|
| 278 |
4 |
sergeykhbr |
case OPCODE_C_SWSP:
|
| 279 |
|
|
wb_isa_type[ISA_S_type] = 1;
|
| 280 |
|
|
wb_dec[Instr_SW] = 1;
|
| 281 |
|
|
wb_instr_out(24, 20) = wb_instr(6, 2); // rs2
|
| 282 |
|
|
wb_instr_out(19, 15) = 0x2; // rs1 = sp
|
| 283 |
|
|
wb_instr_out(11, 9) = wb_instr(11, 9);
|
| 284 |
|
|
wb_instr_out(27, 25) = (wb_instr(8, 7), wb_instr[12]);
|
| 285 |
3 |
sergeykhbr |
break;
|
| 286 |
4 |
sergeykhbr |
case OPCODE_C_SD:
|
| 287 |
|
|
wb_isa_type[ISA_S_type] = 1;
|
| 288 |
|
|
wb_dec[Instr_SD] = 1;
|
| 289 |
|
|
wb_instr_out(24, 20) = 0x8 | wb_instr(4, 2); // rs2
|
| 290 |
|
|
wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
|
| 291 |
|
|
wb_instr_out(11, 10) = wb_instr(11, 10);
|
| 292 |
|
|
wb_instr_out(27, 25) = (wb_instr(6, 5), wb_instr[12]);
|
| 293 |
3 |
sergeykhbr |
break;
|
| 294 |
4 |
sergeykhbr |
case OPCODE_C_BNEZ:
|
| 295 |
|
|
wb_isa_type[ISA_SB_type] = 1;
|
| 296 |
|
|
wb_dec[Instr_BNE] = 1;
|
| 297 |
|
|
wb_instr_out(19, 15) = 0x8 | wb_instr(9, 7); // rs1
|
| 298 |
|
|
wb_instr_out(11, 8) = (wb_instr(11, 10), wb_instr(4, 3));
|
| 299 |
|
|
wb_instr_out(27, 25) = (wb_instr(6, 5), wb_instr[2]);
|
| 300 |
|
|
if (wb_instr[12]) {
|
| 301 |
|
|
wb_instr_out(30, 28) = ~0;
|
| 302 |
|
|
wb_instr_out[7] = 1;
|
| 303 |
|
|
wb_instr_out[31] = 1;
|
| 304 |
3 |
sergeykhbr |
}
|
| 305 |
|
|
break;
|
| 306 |
4 |
sergeykhbr |
case OPCODE_C_SDSP:
|
| 307 |
|
|
wb_isa_type[ISA_S_type] = 1;
|
| 308 |
|
|
wb_dec[Instr_SD] = 1;
|
| 309 |
|
|
wb_instr_out(24, 20) = wb_instr(6, 2); // rs2
|
| 310 |
|
|
wb_instr_out(19, 15) = 0x2; // rs1 = sp
|
| 311 |
|
|
wb_instr_out(11, 10) = wb_instr(11, 10);
|
| 312 |
|
|
wb_instr_out(28, 25) = (wb_instr(9, 7), wb_instr[12]);
|
| 313 |
3 |
sergeykhbr |
break;
|
| 314 |
|
|
default:
|
| 315 |
|
|
w_error = true;
|
| 316 |
|
|
}
|
| 317 |
4 |
sergeykhbr |
} else {
|
| 318 |
|
|
wb_opcode1 = wb_instr(6, 2);
|
| 319 |
|
|
wb_opcode2 = wb_instr(14, 12);
|
| 320 |
|
|
switch (wb_opcode1) {
|
| 321 |
|
|
case OPCODE_ADD:
|
| 322 |
|
|
wb_isa_type[ISA_R_type] = 1;
|
| 323 |
|
|
switch (wb_opcode2) {
|
| 324 |
|
|
case 0:
|
| 325 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 326 |
|
|
wb_dec[Instr_ADD] = 1;
|
| 327 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 328 |
|
|
wb_dec[Instr_MUL] = 1;
|
| 329 |
|
|
} else if (wb_instr(31, 25) == 0x20) {
|
| 330 |
|
|
wb_dec[Instr_SUB] = 1;
|
| 331 |
|
|
} else {
|
| 332 |
|
|
w_error = true;
|
| 333 |
|
|
}
|
| 334 |
|
|
break;
|
| 335 |
|
|
case 0x1:
|
| 336 |
|
|
wb_dec[Instr_SLL] = 1;
|
| 337 |
|
|
break;
|
| 338 |
|
|
case 0x2:
|
| 339 |
|
|
wb_dec[Instr_SLT] = 1;
|
| 340 |
|
|
break;
|
| 341 |
|
|
case 0x3:
|
| 342 |
|
|
wb_dec[Instr_SLTU] = 1;
|
| 343 |
|
|
break;
|
| 344 |
|
|
case 0x4:
|
| 345 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 346 |
|
|
wb_dec[Instr_XOR] = 1;
|
| 347 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 348 |
|
|
wb_dec[Instr_DIV] = 1;
|
| 349 |
|
|
} else {
|
| 350 |
|
|
w_error = true;
|
| 351 |
|
|
}
|
| 352 |
|
|
break;
|
| 353 |
|
|
case 0x5:
|
| 354 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 355 |
|
|
wb_dec[Instr_SRL] = 1;
|
| 356 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 357 |
|
|
wb_dec[Instr_DIVU] = 1;
|
| 358 |
|
|
} else if (wb_instr(31, 25) == 0x20) {
|
| 359 |
|
|
wb_dec[Instr_SRA] = 1;
|
| 360 |
|
|
} else {
|
| 361 |
|
|
w_error = true;
|
| 362 |
|
|
}
|
| 363 |
|
|
break;
|
| 364 |
|
|
case 0x6:
|
| 365 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 366 |
|
|
wb_dec[Instr_OR] = 1;
|
| 367 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 368 |
|
|
wb_dec[Instr_REM] = 1;
|
| 369 |
|
|
} else {
|
| 370 |
|
|
w_error = true;
|
| 371 |
|
|
}
|
| 372 |
|
|
break;
|
| 373 |
|
|
case 0x7:
|
| 374 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 375 |
|
|
wb_dec[Instr_AND] = 1;
|
| 376 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 377 |
|
|
wb_dec[Instr_REMU] = 1;
|
| 378 |
|
|
} else {
|
| 379 |
|
|
w_error = true;
|
| 380 |
|
|
}
|
| 381 |
|
|
break;
|
| 382 |
|
|
default:
|
| 383 |
|
|
w_error = true;
|
| 384 |
|
|
}
|
| 385 |
3 |
sergeykhbr |
break;
|
| 386 |
4 |
sergeykhbr |
case OPCODE_ADDI:
|
| 387 |
|
|
wb_isa_type[ISA_I_type] = 1;
|
| 388 |
|
|
switch (wb_opcode2) {
|
| 389 |
|
|
case 0:
|
| 390 |
|
|
wb_dec[Instr_ADDI] = 1;
|
| 391 |
|
|
break;
|
| 392 |
|
|
case 0x1:
|
| 393 |
|
|
wb_dec[Instr_SLLI] = 1;
|
| 394 |
|
|
break;
|
| 395 |
|
|
case 0x2:
|
| 396 |
|
|
wb_dec[Instr_SLTI] = 1;
|
| 397 |
|
|
break;
|
| 398 |
|
|
case 0x3:
|
| 399 |
|
|
wb_dec[Instr_SLTIU] = 1;
|
| 400 |
|
|
break;
|
| 401 |
|
|
case 0x4:
|
| 402 |
|
|
wb_dec[Instr_XORI] = 1;
|
| 403 |
|
|
break;
|
| 404 |
|
|
case 0x5:
|
| 405 |
|
|
if (wb_instr(31, 26) == 0x00) {
|
| 406 |
|
|
wb_dec[Instr_SRLI] = 1;
|
| 407 |
|
|
} else if (wb_instr(31, 26) == 0x10) {
|
| 408 |
|
|
wb_dec[Instr_SRAI] = 1;
|
| 409 |
|
|
} else {
|
| 410 |
|
|
w_error = true;
|
| 411 |
|
|
}
|
| 412 |
|
|
break;
|
| 413 |
|
|
case 0x6:
|
| 414 |
|
|
wb_dec[Instr_ORI] = 1;
|
| 415 |
|
|
break;
|
| 416 |
|
|
case 7:
|
| 417 |
|
|
wb_dec[Instr_ANDI] = 1;
|
| 418 |
|
|
break;
|
| 419 |
|
|
default:
|
| 420 |
|
|
w_error = true;
|
| 421 |
|
|
}
|
| 422 |
3 |
sergeykhbr |
break;
|
| 423 |
4 |
sergeykhbr |
case OPCODE_ADDIW:
|
| 424 |
|
|
wb_isa_type[ISA_I_type] = 1;
|
| 425 |
|
|
switch (wb_opcode2) {
|
| 426 |
|
|
case 0:
|
| 427 |
|
|
wb_dec[Instr_ADDIW] = 1;
|
| 428 |
|
|
break;
|
| 429 |
|
|
case 0x1:
|
| 430 |
|
|
wb_dec[Instr_SLLIW] = 1;
|
| 431 |
|
|
break;
|
| 432 |
|
|
case 0x5:
|
| 433 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 434 |
|
|
wb_dec[Instr_SRLIW] = 1;
|
| 435 |
|
|
} else if (wb_instr(31, 25) == 0x20) {
|
| 436 |
|
|
wb_dec[Instr_SRAIW] = 1;
|
| 437 |
|
|
} else {
|
| 438 |
|
|
w_error = true;
|
| 439 |
|
|
}
|
| 440 |
|
|
break;
|
| 441 |
|
|
default:
|
| 442 |
3 |
sergeykhbr |
w_error = true;
|
| 443 |
|
|
}
|
| 444 |
|
|
break;
|
| 445 |
4 |
sergeykhbr |
case OPCODE_ADDW:
|
| 446 |
|
|
wb_isa_type[ISA_R_type] = 1;
|
| 447 |
|
|
switch (wb_opcode2) {
|
| 448 |
|
|
case 0:
|
| 449 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 450 |
|
|
wb_dec[Instr_ADDW] = 1;
|
| 451 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 452 |
|
|
wb_dec[Instr_MULW] = 1;
|
| 453 |
|
|
} else if (wb_instr(31, 25) == 0x20) {
|
| 454 |
|
|
wb_dec[Instr_SUBW] = 1;
|
| 455 |
|
|
} else {
|
| 456 |
|
|
w_error = true;
|
| 457 |
|
|
}
|
| 458 |
|
|
break;
|
| 459 |
|
|
case 0x1:
|
| 460 |
|
|
wb_dec[Instr_SLLW] = 1;
|
| 461 |
|
|
break;
|
| 462 |
|
|
case 0x4:
|
| 463 |
|
|
if (wb_instr(31, 25) == 0x01) {
|
| 464 |
|
|
wb_dec[Instr_DIVW] = 1;
|
| 465 |
|
|
} else {
|
| 466 |
|
|
w_error = true;
|
| 467 |
|
|
}
|
| 468 |
|
|
break;
|
| 469 |
|
|
case 0x5:
|
| 470 |
|
|
if (wb_instr(31, 25) == 0x00) {
|
| 471 |
|
|
wb_dec[Instr_SRLW] = 1;
|
| 472 |
|
|
} else if (wb_instr(31, 25) == 0x01) {
|
| 473 |
|
|
wb_dec[Instr_DIVUW] = 1;
|
| 474 |
|
|
} else if (wb_instr(31, 25) == 0x20) {
|
| 475 |
|
|
wb_dec[Instr_SRAW] = 1;
|
| 476 |
|
|
} else {
|
| 477 |
|
|
w_error = true;
|
| 478 |
|
|
}
|
| 479 |
|
|
break;
|
| 480 |
|
|
case 0x6:
|
| 481 |
|
|
if (wb_instr(31, 25) == 0x01) {
|
| 482 |
|
|
wb_dec[Instr_REMW] = 1;
|
| 483 |
|
|
} else {
|
| 484 |
|
|
w_error = true;
|
| 485 |
|
|
}
|
| 486 |
|
|
break;
|
| 487 |
|
|
case 0x7:
|
| 488 |
|
|
if (wb_instr(31, 25) == 0x01) {
|
| 489 |
|
|
wb_dec[Instr_REMUW] = 1;
|
| 490 |
|
|
} else {
|
| 491 |
|
|
w_error = true;
|
| 492 |
|
|
}
|
| 493 |
|
|
break;
|
| 494 |
|
|
default:
|
| 495 |
3 |
sergeykhbr |
w_error = true;
|
| 496 |
|
|
}
|
| 497 |
|
|
break;
|
| 498 |
4 |
sergeykhbr |
case OPCODE_AUIPC:
|
| 499 |
|
|
wb_isa_type[ISA_U_type] = 1;
|
| 500 |
|
|
wb_dec[Instr_AUIPC] = 1;
|
| 501 |
3 |
sergeykhbr |
break;
|
| 502 |
4 |
sergeykhbr |
case OPCODE_BEQ:
|
| 503 |
|
|
wb_isa_type[ISA_SB_type] = 1;
|
| 504 |
|
|
switch (wb_opcode2) {
|
| 505 |
|
|
case 0:
|
| 506 |
|
|
wb_dec[Instr_BEQ] = 1;
|
| 507 |
|
|
break;
|
| 508 |
|
|
case 1:
|
| 509 |
|
|
wb_dec[Instr_BNE] = 1;
|
| 510 |
|
|
break;
|
| 511 |
|
|
case 4:
|
| 512 |
|
|
wb_dec[Instr_BLT] = 1;
|
| 513 |
|
|
break;
|
| 514 |
|
|
case 5:
|
| 515 |
|
|
wb_dec[Instr_BGE] = 1;
|
| 516 |
|
|
break;
|
| 517 |
|
|
case 6:
|
| 518 |
|
|
wb_dec[Instr_BLTU] = 1;
|
| 519 |
|
|
break;
|
| 520 |
|
|
case 7:
|
| 521 |
|
|
wb_dec[Instr_BGEU] = 1;
|
| 522 |
|
|
break;
|
| 523 |
|
|
default:
|
| 524 |
3 |
sergeykhbr |
w_error = true;
|
| 525 |
|
|
}
|
| 526 |
|
|
break;
|
| 527 |
4 |
sergeykhbr |
case OPCODE_JAL:
|
| 528 |
|
|
wb_isa_type[ISA_UJ_type] = 1;
|
| 529 |
|
|
wb_dec[Instr_JAL] = 1;
|
| 530 |
|
|
break;
|
| 531 |
|
|
case OPCODE_JALR:
|
| 532 |
|
|
wb_isa_type[ISA_I_type] = 1;
|
| 533 |
|
|
switch (wb_opcode2) {
|
| 534 |
|
|
case 0:
|
| 535 |
|
|
wb_dec[Instr_JALR] = 1;
|
| 536 |
|
|
break;
|
| 537 |
|
|
default:
|
| 538 |
3 |
sergeykhbr |
w_error = true;
|
| 539 |
|
|
}
|
| 540 |
|
|
break;
|
| 541 |
4 |
sergeykhbr |
case OPCODE_LB:
|
| 542 |
|
|
wb_isa_type[ISA_I_type] = 1;
|
| 543 |
|
|
switch (wb_opcode2) {
|
| 544 |
|
|
case 0:
|
| 545 |
|
|
wb_dec[Instr_LB] = 1;
|
| 546 |
|
|
break;
|
| 547 |
|
|
case 1:
|
| 548 |
|
|
wb_dec[Instr_LH] = 1;
|
| 549 |
|
|
break;
|
| 550 |
|
|
case 2:
|
| 551 |
|
|
wb_dec[Instr_LW] = 1;
|
| 552 |
|
|
break;
|
| 553 |
|
|
case 3:
|
| 554 |
|
|
wb_dec[Instr_LD] = 1;
|
| 555 |
|
|
break;
|
| 556 |
|
|
case 4:
|
| 557 |
|
|
wb_dec[Instr_LBU] = 1;
|
| 558 |
|
|
break;
|
| 559 |
|
|
case 5:
|
| 560 |
|
|
wb_dec[Instr_LHU] = 1;
|
| 561 |
|
|
break;
|
| 562 |
|
|
case 6:
|
| 563 |
|
|
wb_dec[Instr_LWU] = 1;
|
| 564 |
|
|
break;
|
| 565 |
|
|
default:
|
| 566 |
3 |
sergeykhbr |
w_error = true;
|
| 567 |
|
|
}
|
| 568 |
|
|
break;
|
| 569 |
4 |
sergeykhbr |
case OPCODE_LUI:
|
| 570 |
|
|
wb_isa_type[ISA_U_type] = 1;
|
| 571 |
|
|
wb_dec[Instr_LUI] = 1;
|
| 572 |
|
|
break;
|
| 573 |
|
|
case OPCODE_SB:
|
| 574 |
|
|
wb_isa_type[ISA_S_type] = 1;
|
| 575 |
|
|
switch (wb_opcode2) {
|
| 576 |
|
|
case 0:
|
| 577 |
|
|
wb_dec[Instr_SB] = 1;
|
| 578 |
|
|
break;
|
| 579 |
|
|
case 1:
|
| 580 |
|
|
wb_dec[Instr_SH] = 1;
|
| 581 |
|
|
break;
|
| 582 |
|
|
case 2:
|
| 583 |
|
|
wb_dec[Instr_SW] = 1;
|
| 584 |
|
|
break;
|
| 585 |
|
|
case 3:
|
| 586 |
|
|
wb_dec[Instr_SD] = 1;
|
| 587 |
|
|
break;
|
| 588 |
|
|
default:
|
| 589 |
3 |
sergeykhbr |
w_error = true;
|
| 590 |
|
|
}
|
| 591 |
|
|
break;
|
| 592 |
4 |
sergeykhbr |
case OPCODE_CSRR:
|
| 593 |
|
|
wb_isa_type[ISA_I_type] = 1;
|
| 594 |
|
|
switch (wb_opcode2) {
|
| 595 |
|
|
case 0:
|
| 596 |
|
|
if (wb_instr == 0x00000073) {
|
| 597 |
|
|
wb_dec[Instr_ECALL] = 1;
|
| 598 |
|
|
} else if (wb_instr == 0x00100073) {
|
| 599 |
|
|
wb_dec[Instr_EBREAK] = 1;
|
| 600 |
|
|
} else if (wb_instr == 0x00200073) {
|
| 601 |
|
|
wb_dec[Instr_URET] = 1;
|
| 602 |
|
|
} else if (wb_instr == 0x10200073) {
|
| 603 |
|
|
wb_dec[Instr_SRET] = 1;
|
| 604 |
|
|
} else if (wb_instr == 0x20200073) {
|
| 605 |
|
|
wb_dec[Instr_HRET] = 1;
|
| 606 |
|
|
} else if (wb_instr == 0x30200073) {
|
| 607 |
|
|
wb_dec[Instr_MRET] = 1;
|
| 608 |
|
|
} else {
|
| 609 |
|
|
w_error = true;
|
| 610 |
|
|
}
|
| 611 |
|
|
break;
|
| 612 |
|
|
case 1:
|
| 613 |
|
|
wb_dec[Instr_CSRRW] = 1;
|
| 614 |
|
|
break;
|
| 615 |
|
|
case 2:
|
| 616 |
|
|
wb_dec[Instr_CSRRS] = 1;
|
| 617 |
|
|
break;
|
| 618 |
|
|
case 3:
|
| 619 |
|
|
wb_dec[Instr_CSRRC] = 1;
|
| 620 |
|
|
break;
|
| 621 |
|
|
case 5:
|
| 622 |
|
|
wb_dec[Instr_CSRRWI] = 1;
|
| 623 |
|
|
break;
|
| 624 |
|
|
case 6:
|
| 625 |
|
|
wb_dec[Instr_CSRRSI] = 1;
|
| 626 |
|
|
break;
|
| 627 |
|
|
case 7:
|
| 628 |
|
|
wb_dec[Instr_CSRRCI] = 1;
|
| 629 |
|
|
break;
|
| 630 |
|
|
default:
|
| 631 |
|
|
w_error = true;
|
| 632 |
|
|
}
|
| 633 |
3 |
sergeykhbr |
break;
|
| 634 |
4 |
sergeykhbr |
case OPCODE_FENCE:
|
| 635 |
|
|
switch (wb_opcode2) {
|
| 636 |
|
|
case 0:
|
| 637 |
|
|
wb_dec[Instr_FENCE] = 1;
|
| 638 |
|
|
break;
|
| 639 |
|
|
case 1:
|
| 640 |
|
|
wb_dec[Instr_FENCE_I] = 1;
|
| 641 |
|
|
break;
|
| 642 |
|
|
default:
|
| 643 |
3 |
sergeykhbr |
w_error = true;
|
| 644 |
|
|
}
|
| 645 |
|
|
break;
|
| 646 |
4 |
sergeykhbr |
|
| 647 |
3 |
sergeykhbr |
default:
|
| 648 |
|
|
w_error = true;
|
| 649 |
|
|
}
|
| 650 |
4 |
sergeykhbr |
wb_instr_out = wb_instr;
|
| 651 |
|
|
} // compressed/!compressed
|
| 652 |
3 |
sergeykhbr |
|
| 653 |
|
|
if (i_f_valid.read()) {
|
| 654 |
|
|
v.valid = 1;
|
| 655 |
|
|
v.pc = i_f_pc;
|
| 656 |
4 |
sergeykhbr |
v.instr = wb_instr_out;
|
| 657 |
|
|
v.compressed = w_compressed;
|
| 658 |
3 |
sergeykhbr |
|
| 659 |
|
|
v.isa_type = wb_isa_type;
|
| 660 |
|
|
v.instr_vec = wb_dec;
|
| 661 |
|
|
v.memop_store = (wb_dec[Instr_SD] | wb_dec[Instr_SW]
|
| 662 |
|
|
| wb_dec[Instr_SH] | wb_dec[Instr_SB]).to_bool();
|
| 663 |
|
|
v.memop_load = (wb_dec[Instr_LD] | wb_dec[Instr_LW]
|
| 664 |
|
|
| wb_dec[Instr_LH] | wb_dec[Instr_LB]
|
| 665 |
|
|
| wb_dec[Instr_LWU] | wb_dec[Instr_LHU]
|
| 666 |
|
|
| wb_dec[Instr_LBU]).to_bool();
|
| 667 |
|
|
v.memop_sign_ext = (wb_dec[Instr_LD] | wb_dec[Instr_LW]
|
| 668 |
|
|
| wb_dec[Instr_LH] | wb_dec[Instr_LB]).to_bool();
|
| 669 |
|
|
if (wb_dec[Instr_LD] || wb_dec[Instr_SD]) {
|
| 670 |
|
|
v.memop_size = MEMOP_8B;
|
| 671 |
|
|
} else if (wb_dec[Instr_LW] || wb_dec[Instr_LWU] || wb_dec[Instr_SW]) {
|
| 672 |
|
|
v.memop_size = MEMOP_4B;
|
| 673 |
|
|
} else if (wb_dec[Instr_LH] || wb_dec[Instr_LHU] || wb_dec[Instr_SH]) {
|
| 674 |
|
|
v.memop_size = MEMOP_2B;
|
| 675 |
|
|
} else {
|
| 676 |
|
|
v.memop_size = MEMOP_1B;
|
| 677 |
|
|
}
|
| 678 |
|
|
v.unsigned_op = (wb_dec[Instr_DIVU] | wb_dec[Instr_REMU] |
|
| 679 |
|
|
wb_dec[Instr_DIVUW] | wb_dec[Instr_REMUW]).to_bool();
|
| 680 |
|
|
|
| 681 |
|
|
v.rv32 = (wb_dec[Instr_ADDW] | wb_dec[Instr_ADDIW]
|
| 682 |
|
|
| wb_dec[Instr_SLLW] | wb_dec[Instr_SLLIW] | wb_dec[Instr_SRAW]
|
| 683 |
|
|
| wb_dec[Instr_SRAIW]
|
| 684 |
|
|
| wb_dec[Instr_SRLW] | wb_dec[Instr_SRLIW] | wb_dec[Instr_SUBW]
|
| 685 |
|
|
| wb_dec[Instr_DIVW] | wb_dec[Instr_DIVUW] | wb_dec[Instr_MULW]
|
| 686 |
|
|
| wb_dec[Instr_REMW] | wb_dec[Instr_REMUW]).to_bool();
|
| 687 |
|
|
|
| 688 |
|
|
v.instr_unimplemented = w_error;
|
| 689 |
|
|
} else if (!i_any_hold.read()) {
|
| 690 |
|
|
v.valid = 0;
|
| 691 |
|
|
}
|
| 692 |
|
|
w_o_valid = r.valid.read() && !i_any_hold.read();
|
| 693 |
|
|
|
| 694 |
|
|
if (!i_nrst.read()) {
|
| 695 |
|
|
v.valid = false;
|
| 696 |
|
|
v.pc = 0;
|
| 697 |
|
|
v.instr = 0;
|
| 698 |
|
|
v.isa_type = 0;
|
| 699 |
|
|
v.instr_vec = 0;
|
| 700 |
|
|
v.memop_store = 0;
|
| 701 |
|
|
v.memop_load = 0;
|
| 702 |
|
|
v.memop_sign_ext = 0;
|
| 703 |
|
|
v.memop_size = MEMOP_1B;
|
| 704 |
|
|
v.unsigned_op = 0;
|
| 705 |
|
|
v.rv32 = 0;
|
| 706 |
4 |
sergeykhbr |
v.compressed = 0;
|
| 707 |
3 |
sergeykhbr |
|
| 708 |
|
|
v.instr_unimplemented = !wb_dec.or_reduce();
|
| 709 |
|
|
}
|
| 710 |
|
|
|
| 711 |
|
|
o_valid = w_o_valid;
|
| 712 |
|
|
o_pc = r.pc;
|
| 713 |
|
|
o_instr = r.instr;
|
| 714 |
|
|
o_memop_load = r.memop_load;
|
| 715 |
|
|
o_memop_store = r.memop_store;
|
| 716 |
|
|
o_memop_sign_ext = r.memop_sign_ext;
|
| 717 |
|
|
o_memop_size = r.memop_size;
|
| 718 |
|
|
o_unsigned_op = r.unsigned_op;
|
| 719 |
|
|
o_rv32 = r.rv32;
|
| 720 |
4 |
sergeykhbr |
o_compressed = r.compressed;
|
| 721 |
3 |
sergeykhbr |
o_isa_type = r.isa_type;
|
| 722 |
|
|
o_instr_vec = r.instr_vec;
|
| 723 |
|
|
o_exception = r.instr_unimplemented;
|
| 724 |
|
|
}
|
| 725 |
|
|
|
| 726 |
|
|
void InstrDecoder::registers() {
|
| 727 |
|
|
r = v;
|
| 728 |
|
|
}
|
| 729 |
|
|
|
| 730 |
|
|
} // namespace debugger
|
| 731 |
|
|
|
