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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief CPU Instruction Decoder stage.
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*/
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#ifndef __DEBUGGER_RIVERLIB_DECODER_H__
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#define __DEBUGGER_RIVERLIB_DECODER_H__
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#include <systemc.h>
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#include "../river_cfg.h"
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namespace debugger {
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const uint8_t OPCODE_LB = 0x00; // 00000: LB, LH, LW, LD, LBU, LHU, LWU
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const uint8_t OPCODE_FENCE = 0x03; // 00011: FENCE, FENCE_I
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const uint8_t OPCODE_ADDI = 0x04; // 00100: ADDI, ANDI, ORI, SLLI, SLTI, SLTIU, SRAI, SRLI, XORI
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const uint8_t OPCODE_AUIPC = 0x05; // 00101: AUIPC
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const uint8_t OPCODE_ADDIW = 0x06; // 00110: ADDIW, SLLIW, SRAIW, SRLIW
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const uint8_t OPCODE_SB = 0x08; // 01000: SB, SH, SW, SD
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const uint8_t OPCODE_ADD = 0x0C; // 01100: ADD, AND, OR, SLT, SLTU, SLL, SRA, SRL, SUB, XOR, DIV, DIVU, MUL, REM, REMU
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const uint8_t OPCODE_LUI = 0x0D; // 01101: LUI
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const uint8_t OPCODE_ADDW = 0x0E; // 01110: ADDW, SLLW, SRAW, SRLW, SUBW, DIVW, DIVUW, MULW, REMW, REMUW
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const uint8_t OPCODE_BEQ = 0x18; // 11000: BEQ, BNE, BLT, BGE, BLTU, BGEU
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const uint8_t OPCODE_JALR = 0x19; // 11001: JALR
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const uint8_t OPCODE_JAL = 0x1B; // 11011: JAL
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const uint8_t OPCODE_CSRR = 0x1C; // 11100: CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI, URET, SRET, HRET, MRET
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SC_MODULE(InstrDecoder) {
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sc_in<bool> i_clk;
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sc_in<bool> i_nrst; // Reset active low
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sc_in<bool> i_any_hold; // Hold pipeline by any reason
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sc_in<bool> i_f_valid; // Fetch input valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_f_pc; // Fetched pc
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sc_in<sc_uint<32>> i_f_instr; // Fetched instruction value
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sc_out<bool> o_valid; // Current output values are valid
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Current instruction pointer value
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sc_out<sc_uint<32>> o_instr; // Current instruction value
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sc_out<bool> o_memop_store; // Store to memory operation
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sc_out<bool> o_memop_load; // Load from memoru operation
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sc_out<bool> o_memop_sign_ext; // Load memory value with sign extending
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sc_out<sc_uint<2>> o_memop_size; // Memory transaction size
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sc_out<bool> o_rv32; // 32-bits instruction
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sc_out<bool> o_unsigned_op; // Unsigned operands
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sc_out<sc_bv<ISA_Total>> o_isa_type; // Instruction format accordingly with ISA
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sc_out<sc_bv<Instr_Total>> o_instr_vec; // One bit per decoded instruction bus
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sc_out<bool> o_exception;
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void comb();
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void registers();
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SC_HAS_PROCESS(InstrDecoder);
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InstrDecoder(sc_module_name name_);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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struct RegistersType {
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sc_signal<bool> valid;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_bv<ISA_Total> isa_type;
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sc_bv<Instr_Total> instr_vec;
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sc_signal<sc_uint<32>> instr;
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sc_signal<bool> memop_store;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_sign_ext;
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sc_signal<sc_uint<2>> memop_size;
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sc_signal<bool> unsigned_op;
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sc_signal<bool> rv32;
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sc_signal<bool> instr_unimplemented;
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} v, r;
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};
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_DECODER_H__
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