1 |
4 |
sergeykhbr |
/*
|
2 |
|
|
* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
|
3 |
|
|
*
|
4 |
|
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
5 |
|
|
* you may not use this file except in compliance with the License.
|
6 |
|
|
* You may obtain a copy of the License at
|
7 |
|
|
*
|
8 |
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
9 |
|
|
*
|
10 |
|
|
* Unless required by applicable law or agreed to in writing, software
|
11 |
|
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
12 |
|
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
13 |
|
|
* See the License for the specific language governing permissions and
|
14 |
|
|
* limitations under the License.
|
15 |
3 |
sergeykhbr |
*/
|
16 |
|
|
|
17 |
|
|
#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
|
18 |
|
|
#define __DEBUGGER_RIVERLIB_EXECUTE_H__
|
19 |
|
|
|
20 |
|
|
#include <systemc.h>
|
21 |
|
|
#include "../river_cfg.h"
|
22 |
|
|
#include "arith/int_div.h"
|
23 |
|
|
#include "arith/int_mul.h"
|
24 |
|
|
#include "arith/shift.h"
|
25 |
|
|
|
26 |
|
|
namespace debugger {
|
27 |
|
|
|
28 |
|
|
SC_MODULE(InstrExecute) {
|
29 |
|
|
sc_in<bool> i_clk;
|
30 |
|
|
sc_in<bool> i_nrst; // Reset active LOW
|
31 |
|
|
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
|
32 |
|
|
sc_in<bool> i_d_valid; // Decoded instruction is valid
|
33 |
|
|
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
|
34 |
|
|
sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
|
35 |
|
|
sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
|
36 |
|
|
sc_in<bool> i_memop_store; // Store to memory operation
|
37 |
|
|
sc_in<bool> i_memop_load; // Load from memoru operation
|
38 |
|
|
sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
|
39 |
|
|
sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
|
40 |
|
|
sc_in<bool> i_unsigned_op; // Unsigned operands
|
41 |
|
|
sc_in<bool> i_rv32; // 32-bits instruction
|
42 |
4 |
sergeykhbr |
sc_in<bool> i_compressed; // C-extension (2-bytes length)
|
43 |
3 |
sergeykhbr |
sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
|
44 |
|
|
sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
|
45 |
|
|
sc_in<bool> i_ie; // Interrupt enable bit
|
46 |
|
|
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mtvec; // Interrupt descriptor table
|
47 |
|
|
sc_in<sc_uint<2>> i_mode; // Current processor mode
|
48 |
|
|
sc_in<bool> i_break_mode; // Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
|
49 |
|
|
sc_in<bool> i_unsup_exception; // Unsupported instruction exception
|
50 |
|
|
sc_in<bool> i_ext_irq; // External interrupt from PLIC (todo: timer & software interrupts)
|
51 |
|
|
sc_in<bool> i_dport_npc_write; // Write npc value from debug port
|
52 |
|
|
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
|
53 |
|
|
|
54 |
|
|
sc_out<sc_uint<5>> o_radr1; // Integer register index 1
|
55 |
|
|
sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
|
56 |
|
|
sc_out<sc_uint<5>> o_radr2; // Integer register index 2
|
57 |
|
|
sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
|
58 |
|
|
sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
|
59 |
|
|
sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
|
60 |
|
|
sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
|
61 |
|
|
sc_out<bool> o_xret; // XRET instruction: MRET, URET or other.
|
62 |
|
|
sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
|
63 |
|
|
sc_out<bool> o_csr_wena; // Write new CSR value
|
64 |
|
|
sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
|
65 |
|
|
sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
|
66 |
|
|
sc_out<bool> o_trap_ena; // Trap occurs pulse
|
67 |
|
|
sc_out<sc_uint<5>> o_trap_code; // bit[4] : 1=interrupt; 0=exception; bits[3:0]=code
|
68 |
|
|
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_trap_pc; // trap on pc
|
69 |
|
|
|
70 |
|
|
sc_out<bool> o_memop_sign_ext; // Load data with sign extending
|
71 |
|
|
sc_out<bool> o_memop_load; // Load data instruction
|
72 |
|
|
sc_out<bool> o_memop_store; // Store data instruction
|
73 |
|
|
sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
|
74 |
|
|
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
|
75 |
|
|
|
76 |
|
|
sc_out<bool> o_valid; // Output is valid
|
77 |
|
|
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
|
78 |
|
|
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
|
79 |
|
|
sc_out<sc_uint<32>> o_instr; // Valid instruction value
|
80 |
|
|
sc_out<bool> o_breakpoint; // ebreak instruction
|
81 |
|
|
sc_out<bool> o_call; // CALL pseudo instruction detected
|
82 |
|
|
sc_out<bool> o_ret; // RET pseudoinstruction detected
|
83 |
|
|
|
84 |
|
|
void comb();
|
85 |
|
|
void registers();
|
86 |
|
|
|
87 |
|
|
SC_HAS_PROCESS(InstrExecute);
|
88 |
|
|
|
89 |
|
|
InstrExecute(sc_module_name name_);
|
90 |
|
|
virtual ~InstrExecute();
|
91 |
|
|
|
92 |
|
|
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
|
93 |
|
|
|
94 |
|
|
private:
|
95 |
|
|
enum EMultiCycleInstruction {
|
96 |
|
|
Multi_MUL,
|
97 |
|
|
Multi_DIV,
|
98 |
|
|
Multi_Total
|
99 |
|
|
};
|
100 |
|
|
|
101 |
|
|
struct multi_arith_type {
|
102 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> arr[Multi_Total];
|
103 |
|
|
};
|
104 |
|
|
|
105 |
|
|
struct RegistersType {
|
106 |
|
|
sc_signal<bool> d_valid; // Valid decoded instruction latch
|
107 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
|
108 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
|
109 |
|
|
sc_signal<sc_uint<32>> instr;
|
110 |
|
|
sc_uint<5> res_addr;
|
111 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> res_val;
|
112 |
|
|
sc_signal<bool> memop_load;
|
113 |
|
|
sc_signal<bool> memop_store;
|
114 |
|
|
bool memop_sign_ext;
|
115 |
|
|
sc_uint<2> memop_size;
|
116 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
|
117 |
|
|
|
118 |
|
|
sc_signal<sc_uint<5>> multi_res_addr; // latched output reg. address while multi-cycle instruction
|
119 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_pc; // latched pc-value while multi-cycle instruction
|
120 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_npc; // latched npc-value while multi-cycle instruction
|
121 |
|
|
sc_signal<sc_uint<32>> multi_instr; // Multi-cycle instruction is under processing
|
122 |
|
|
sc_signal<bool> multi_ena[Multi_Total]; // Enable pulse for Operation that takes more than 1 clock
|
123 |
|
|
sc_signal<bool> multi_rv32; // Long operation with 32-bits operands
|
124 |
|
|
sc_signal<bool> multi_unsigned; // Long operation with unsiged operands
|
125 |
|
|
sc_signal<bool> multi_residual_high; // Flag for Divider module: 0=divsion output; 1=residual output
|
126 |
|
|
// Flag for multiplier: 0=usual; 1=get high bits
|
127 |
|
|
sc_signal<bool> multiclock_ena;
|
128 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> multi_a1; // Multi-cycle operand 1
|
129 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> multi_a2; // Multi-cycle operand 2
|
130 |
|
|
|
131 |
|
|
sc_signal<sc_uint<5>> hazard_addr0; // Updated register address on previous step
|
132 |
|
|
sc_signal<sc_uint<5>> hazard_addr1; // Updated register address on pre-previous step
|
133 |
|
|
sc_signal<sc_uint<2>> hazard_depth; // Number of modificated registers that wasn't done yet
|
134 |
|
|
|
135 |
|
|
sc_signal<bool> ext_irq_pulser; // Form 1 clock pulse from strob
|
136 |
|
|
sc_signal<bool> trap_ena; // Trap occur, switch mode
|
137 |
|
|
sc_signal<bool> breakpoint;
|
138 |
|
|
sc_uint<5> trap_code_waiting; // To avoid multi-cycle instruction collision
|
139 |
|
|
sc_signal<sc_uint<5>> trap_code; // bit[4] : 1 = interrupt; 0 = exception
|
140 |
|
|
// bit[3:0] : trap code
|
141 |
|
|
sc_signal<sc_uint<BUS_ADDR_WIDTH>> trap_pc; // pc that caused a trap
|
142 |
|
|
sc_signal<bool> call;
|
143 |
|
|
sc_signal<bool> ret;
|
144 |
|
|
} v, r;
|
145 |
|
|
sc_signal<bool> w_hazard_detected;
|
146 |
|
|
multi_arith_type wb_arith_res;
|
147 |
|
|
sc_signal<bool> w_arith_valid[Multi_Total];
|
148 |
|
|
sc_signal<bool> w_arith_busy[Multi_Total];
|
149 |
|
|
bool w_interrupt;
|
150 |
|
|
bool w_exception;
|
151 |
|
|
bool w_exception_store;
|
152 |
|
|
bool w_exception_load;
|
153 |
|
|
bool w_exception_xret;
|
154 |
|
|
sc_uint<5> wb_exception_code;
|
155 |
|
|
|
156 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_shifter_a1; // Shifters operand 1
|
157 |
|
|
sc_signal<sc_uint<6>> wb_shifter_a2; // Shifters operand 2
|
158 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_sll;
|
159 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_sllw;
|
160 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_srl;
|
161 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_srlw;
|
162 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_sra;
|
163 |
|
|
sc_signal<sc_uint<RISCV_ARCH>> wb_sraw;
|
164 |
|
|
|
165 |
|
|
IntMul *mul0;
|
166 |
|
|
IntDiv *div0;
|
167 |
|
|
Shifter *sh0;
|
168 |
|
|
};
|
169 |
|
|
|
170 |
|
|
|
171 |
|
|
} // namespace debugger
|
172 |
|
|
|
173 |
|
|
#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
|