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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [regibank.cpp] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sergeykhbr
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      Multi-port CPU Integer Registers memory.
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 */
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#include "regibank.h"
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namespace debugger {
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RegIntBank::RegIntBank(sc_module_name name_) : sc_module(name_) {
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    SC_METHOD(comb);
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    sensitive << i_nrst;
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    sensitive << i_radr1;
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    sensitive << i_radr2;
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    sensitive << i_wena;
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    sensitive << i_wdata;
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    sensitive << i_waddr;
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    sensitive << i_dport_ena;
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    sensitive << i_dport_write;
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    sensitive << i_dport_addr;
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    sensitive << i_dport_wdata;
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    sensitive << r.update;
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    SC_METHOD(registers);
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    sensitive << i_clk.pos();
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};
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void RegIntBank::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
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    if (o_vcd) {
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        sc_trace(o_vcd, i_wena, "/top/proc0/regs/i_wena");
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        sc_trace(o_vcd, i_waddr, "/top/proc0/regs/i_waddr");
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        sc_trace(o_vcd, i_wdata, "/top/proc0/regs/i_wdata");
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        sc_trace(o_vcd, r.mem[5], "/top/proc0/regs/r4");
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        sc_trace(o_vcd, o_rdata1, "/top/proc0/regs/o_rdata1");
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        sc_trace(o_vcd, o_rdata2, "/top/proc0/regs/o_rdata2");
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        sc_trace(o_vcd, o_dport_rdata, "/top/proc0/regs/o_dport_rdata");
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    }
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}
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void RegIntBank::comb() {
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    v = r;
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    /** Debug port has higher priority. Collision must be controlled by SW */
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    if (i_dport_ena.read() && i_dport_write.read()) {
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        if (i_dport_addr.read() != 0) {
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            v.mem[i_dport_addr.read()] = i_dport_wdata;
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        }
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    } else if (i_wena.read()) {
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        if (i_waddr.read() != 0) {
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            v.mem[i_waddr.read()] = i_wdata;
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        }
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    }
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    v.update = !r.update.read();
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    if (!i_nrst.read()) {
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        v.mem[0] = 0;
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        for (int i = 1; i < Reg_Total; i++) {
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            v.mem[i] = 0xfeedface;
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        }
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        v.update = 0;
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    }
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    o_rdata1 = r.mem[i_radr1.read()];
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    o_rdata2 = r.mem[i_radr2.read()];
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    o_dport_rdata = r.mem[i_dport_addr.read()];
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    o_ra = r.mem[Reg_ra];
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}
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void RegIntBank::registers() {
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    r = v;
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}
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}  // namespace debugger
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