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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [river_cfg.h] - Blame information for rev 4

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1 4 sergeykhbr 
/*
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 *  Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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 *
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 *  Licensed under the Apache License, Version 2.0 (the "License");
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 *  you may not use this file except in compliance with the License.
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 *  You may obtain a copy of the License at
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 *
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 *      http://www.apache.org/licenses/LICENSE-2.0
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 *
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 *  Unless required by applicable law or agreed to in writing, software
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 *  distributed under the License is distributed on an "AS IS" BASIS,
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 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 *  See the License for the specific language governing permissions and
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 *  limitations under the License.
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 */
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#ifndef __DEBUGGER_RIVER_CFG_H__
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#define __DEBUGGER_RIVER_CFG_H__
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#include <systemc.h>
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namespace debugger {
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static const int RISCV_ARCH     = 64;
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static const int BUS_ADDR_WIDTH = 32;
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static const int BUS_DATA_WIDTH = 64;
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static const int BUS_DATA_BYTES = BUS_DATA_WIDTH / 8;
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static const uint8_t MEMOP_8B = 3;
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static const uint8_t MEMOP_4B = 2;
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static const uint8_t MEMOP_2B = 1;
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static const uint8_t MEMOP_1B = 0;
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static const uint64_t RESET_VECTOR      = 0x0040;
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static const int DBG_FETCH_TRACE_SIZE   = 4;
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/** Number of elements each 2*CFG_ADDR_WIDTH in stack trace buffer: */
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static const int CFG_STACK_TRACE_BUF_SIZE = 32;
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enum EIsaType {
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    ISA_R_type,
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    ISA_I_type,
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    ISA_S_type,
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    ISA_SB_type,
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    ISA_U_type,
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    ISA_UJ_type,
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    ISA_Total
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};
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enum EInstuctionsType {
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    Instr_ADD,
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    Instr_ADDI,
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    Instr_ADDIW,
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    Instr_ADDW,
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    Instr_AND,
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    Instr_ANDI,
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    Instr_AUIPC,
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    Instr_BEQ,
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    Instr_BGE,
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    Instr_BGEU,
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    Instr_BLT,
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    Instr_BLTU,
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    Instr_BNE,
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    Instr_JAL,
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    Instr_JALR,
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    Instr_LB,
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    Instr_LH,
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    Instr_LW,
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    Instr_LD,
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    Instr_LBU,
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    Instr_LHU,
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    Instr_LWU,
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    Instr_LUI,
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    Instr_OR,
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    Instr_ORI,
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    Instr_SLLI,
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    Instr_SLT,
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    Instr_SLTI,
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    Instr_SLTU,
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    Instr_SLTIU,
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    Instr_SLL,
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    Instr_SLLW,
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    Instr_SLLIW,
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    Instr_SRA,
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    Instr_SRAW,
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    Instr_SRAI,
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    Instr_SRAIW,
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    Instr_SRL,
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    Instr_SRLI,
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    Instr_SRLIW,
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    Instr_SRLW,
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    Instr_SB,
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    Instr_SH,
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    Instr_SW,
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    Instr_SD,
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    Instr_SUB,
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    Instr_SUBW,
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    Instr_XOR,
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    Instr_XORI,
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    Instr_CSRRW,
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    Instr_CSRRS,
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    Instr_CSRRC,
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    Instr_CSRRWI,
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    Instr_CSRRCI,
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    Instr_CSRRSI,
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    Instr_URET,
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    Instr_SRET,
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    Instr_HRET,
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    Instr_MRET,
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    Instr_FENCE,
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    Instr_FENCE_I,
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    Instr_DIV,
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    Instr_DIVU,
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    Instr_DIVW,
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    Instr_DIVUW,
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    Instr_MUL,
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    Instr_MULW,
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    Instr_REM,
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    Instr_REMU,
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    Instr_REMW,
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    Instr_REMUW,
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    Instr_ECALL,
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    Instr_EBREAK,
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    Instr_Total
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};
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}  // namespace debugger
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#endif  // __DEBUGGER_RIVER_CFG_H__

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