OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [gui_plugin/] [MainWindow/] [ebreakhandler.cpp] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sergeykhbr
/**
2
 * @file
3
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5
 * @brief      Breakpoint feedback controller.
6
 * @details    This class allows to read/write DSU control operations allowing
7
 *             to correctly continue execution on breakpoints.
8
 */
9
 
10
#include "ebreakhandler.h"
11
#include "coreservices/isrccode.h"
12
 
13
namespace debugger {
14
 
15
EBreakHandler::EBreakHandler(IGui *gui) {
16
    igui_ = gui;
17
    readBr_.make_string("br");
18
    readNpc_.make_string("reg npc");
19
    dsu_sw_br_ = ~0;
20
    dsu_hw_br_ = ~0;
21
}
22
 
23
EBreakHandler::~EBreakHandler() {
24
    igui_->removeFromQueue(static_cast<IGuiCmdHandler *>(this));
25
}
26
 
27
void EBreakHandler::skip() {
28
    igui_->registerCommand(static_cast<IGuiCmdHandler *>(this),
29
                            &readBr_, true);
30
    igui_->registerCommand(static_cast<IGuiCmdHandler *>(this),
31
                            &readNpc_, true);
32
}
33
 
34
void EBreakHandler::handleResponse(AttributeType *req,
35
                                   AttributeType *resp) {
36
    char tstr[128];
37
    AttributeType memWrite;
38
    if (req->is_equal("br")) {
39
        brList_ = *resp;
40
        return;
41
    }
42
    uint64_t br_addr = resp->to_uint64();
43
    uint32_t br_instr = 0;
44
    bool br_hw;
45
    for (unsigned i = 0; i < brList_.size(); i++) {
46
        const AttributeType &br = brList_[i];
47
        if (br_addr == br[BrkList_address].to_uint64()) {
48
            br_instr = br[BrkList_instr].to_int();
49
            br_hw = br[BrkList_hwflag].to_bool();
50
            break;
51
        }
52
    }
53
    if (br_instr == 0) {
54
        return;
55
    }
56
    if (br_hw) {
57
        RISCV_sprintf(tstr, sizeof(tstr),
58
                "write 0x%08" RV_PRI64 "x 8 0x%" RV_PRI64 "x",
59
                dsu_hw_br_, br_addr);
60
    } else {
61
        RISCV_sprintf(tstr, sizeof(tstr),
62
                "write 0x%08" RV_PRI64 "x 16 [0x%" RV_PRI64 "x,0x%x]",
63
                dsu_sw_br_, br_addr, br_instr);
64
    }
65
    memWrite.make_string(tstr);
66
    igui_->registerCommand(NULL, &memWrite, true);
67
}
68
 
69
}  // namespace debugger

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.