OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [iboardsim.h] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sergeykhbr
/**
2
 * @file
3
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5
 * @brief      Simulator of the FPGA board with Ethernet UDP/EDCL interface.
6
 */
7
 
8
#ifndef __DEBUGGER_IBOARD_SIM_H__
9
#define __DEBUGGER_IBOARD_SIM_H__
10
 
11
#include "iface.h"
12
#include "attribute.h"
13
 
14
namespace debugger {
15
 
16
static const char *const IFACE_BOARDSIM = "IBoardSim";
17
 
18
class IBoardSim : public IFace {
19
public:
20
    IBoardSim() : IFace(IFACE_BOARDSIM) {}
21
 
22
    virtual const char *getBrief() {
23
        return "FPGA development board simulator interface";
24
    }
25
 
26
    virtual const char *getDetail() {
27
        return "This interface declares functionality of the emulator of the "
28
               "real hardware. Such emulator allows to develop network "
29
               "interfaces (UDP/EDCL) without connection to the FPGA that "
30
               "significantly simplify debugging.";
31
    }
32
 
33
    virtual void getInfo(AttributeType *attr) =0;
34
};
35
 
36
}  // namespace debugger
37
 
38
#endif  // __DEBUGGER_IBOARD_SIM_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.