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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [irqctrl.cpp] - Blame information for rev 2

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1 2 sergeykhbr 
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      Interrupt controller functional model.
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 */
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#include "api_core.h"
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#include "irqctrl.h"
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namespace debugger {
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IrqController::IrqController(const char *name)  : IService(name) {
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    registerInterface(static_cast<IMemoryOperation *>(this));
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    registerInterface(static_cast<IWire *>(this));
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    registerAttribute("BaseAddress", &baseAddress_);
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    registerAttribute("Length", &length_);
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    registerAttribute("CPU", &cpu_);
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    registerAttribute("CSR_MIPI", &mipi_);
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    registerAttribute("IrqTotal", &irqTotal_);
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    baseAddress_.make_uint64(0);
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    mipi_.make_uint64(0x783);
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    length_.make_uint64(0);
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    cpu_.make_string("");
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    irqTotal_.make_uint64(4);
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    memset(&regs_, 0, sizeof(regs_));
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    regs_.irq_mask = ~0;
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    regs_.irq_lock = 1;
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    irq_wait_unlock = 0;
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}
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IrqController::~IrqController() {
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}
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void IrqController::postinitService() {
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    icpu_ = static_cast<ICpuRiscV *>(
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        RISCV_get_service_iface(cpu_.to_string(), IFACE_CPU_RISCV));
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    if (!icpu_) {
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        RISCV_error("Can't find ICpuRiscV interface %s", cpu_.to_string());
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    }
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}
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void IrqController::b_transport(Axi4TransactionType *trans) {
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    uint64_t mask = (length_.to_uint64() - 1);
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    uint64_t off = ((trans->addr - getBaseAddress()) & mask) / 4;
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    uint32_t t1;
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    trans->response = MemResp_Valid;
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    if (trans->action == MemAction_Write) {
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        for (uint64_t i = 0; i < trans->xsize/4; i++) {
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            if (((trans->wstrb >> 4*i) & 0xFF) == 0) {
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                continue;
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            }
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            switch (off + i) {
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            case 0:
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                regs_.irq_mask = trans->wpayload.b32[i];
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                RISCV_info("Set irq_mask = %08x", trans->wpayload.b32[i]);
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                break;
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            case 1:
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                regs_.irq_pending = trans->wpayload.b32[i];
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                RISCV_info("Set irq_pending = %08x", trans->wpayload.b32[i]);
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                break;
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            case 2:
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                t1 = regs_.irq_pending;
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                regs_.irq_pending &= ~trans->wpayload.b32[i];
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                if (t1 && !regs_.irq_pending) {
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                    icpu_->lowerSignal(CPU_SIGNAL_EXT_IRQ);
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                }
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                RISCV_info("Set irq_clear = %08x", trans->wpayload.b32[i]);
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                break;
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            case 3:
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                regs_.irq_pending |= trans->wpayload.b32[i];
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                RISCV_info("Set irq_rise = %08x", trans->wpayload.b32[i]);
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                break;
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            case 4:
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                regs_.isr_table &= ~0xFFFFFFFFLL;
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                regs_.isr_table |= trans->wpayload.b32[i];
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                RISCV_info("Set irq_handler[31:0] = %08x",
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                            trans->wpayload.b32[i]);
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                break;
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            case 5:
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                regs_.isr_table &= ~0xFFFFFFFF00000000LL;
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                regs_.isr_table |=
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                    (static_cast<uint64_t>(trans->wpayload.b32[i]) << 32);
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                RISCV_info("Set irq_handler[63:32] = %08x",
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                            trans->wpayload.b32[i]);
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                break;
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            case 6:
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                regs_.dbg_cause &= ~0xFFFFFFFFLL;
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                regs_.dbg_cause |= trans->wpayload.b32[i];
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                RISCV_info("Set dbg_cause[31:0] = %08x",
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                            trans->wpayload.b32[i]);
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                break;
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            case 7:
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                regs_.dbg_cause &= ~0xFFFFFFFF00000000LL;
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                regs_.dbg_cause |=
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                    (static_cast<uint64_t>(trans->wpayload.b32[i]) << 32);
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                RISCV_info("Set dbg_cause[63:32] = %08x",
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                            trans->wpayload.b32[i]);
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                break;
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            case 8:
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                regs_.dbg_epc &= ~0xFFFFFFFFLL;
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                regs_.dbg_epc |= trans->wpayload.b32[i];
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                RISCV_info("Set dbg_epc[31:0] = %08x", trans->wpayload.b32[i]);
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                break;
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            case 9:
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                regs_.dbg_epc &= ~0xFFFFFFFF00000000LL;
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                regs_.dbg_epc |=
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                    (static_cast<uint64_t>(trans->wpayload.b32[i]) << 32);
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                RISCV_info("Set dbg_epc[63:32] = %08x",
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                            trans->wpayload.b32[i]);
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                break;
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            case 10:
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                regs_.irq_lock = trans->wpayload.b32[i];
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                RISCV_info("Set irq_ena = %08x", trans->wpayload.b32[i]);
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                if (regs_.irq_lock == 0 && (regs_.irq_pending ||irq_wait_unlock)) {
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                    regs_.irq_pending |= irq_wait_unlock;
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                    icpu_->raiseSignal(CPU_SIGNAL_EXT_IRQ);
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                    irq_wait_unlock = 0;
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                } else if (regs_.irq_lock == 1 && regs_.irq_pending) {
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                    icpu_->lowerSignal(CPU_SIGNAL_EXT_IRQ);
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                }
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                break;
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            case 11:
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                regs_.irq_cause_idx = trans->wpayload.b32[i];
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                RISCV_info("Set irq_cause_idx = %08x", trans->wpayload.b32[i]);
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                break;
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            default:;
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            }
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        }
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    } else {
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        for (uint64_t i = 0; i < trans->xsize/4; i++) {
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            switch (off + i) {
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            case 0:
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                trans->rpayload.b32[i] = regs_.irq_mask;
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                RISCV_info("Get irq_mask = %08x", trans->rpayload.b32[i]);
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                break;
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            case 1:
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                trans->rpayload.b32[i] = regs_.irq_pending;
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                RISCV_info("Get irq_pending = %08x", trans->rpayload.b32[i]);
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                break;
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            case 2:
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                trans->rpayload.b32[i] = 0;
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                RISCV_info("Get irq_clear = %08x", trans->rpayload.b32[i]);
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                break;
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            case 3:
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                trans->rpayload.b32[i] = 0;
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                RISCV_info("Get irq_rise = %08x", trans->rpayload.b32[i]);
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                break;
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            case 4:
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                trans->rpayload.b32[i] =
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                    static_cast<uint32_t>(regs_.isr_table);
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                RISCV_info("Get irq_handler[31:0] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 5:
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                trans->rpayload.b32[i]
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                    = static_cast<uint32_t>(regs_.isr_table >> 32);
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                RISCV_info("Get irq_handler[63:32] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 6:
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                trans->rpayload.b32[i] =
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                    static_cast<uint32_t>(regs_.dbg_cause);
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                RISCV_info("Get dbg_cause[31:0] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 7:
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                trans->rpayload.b32[i] =
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                    static_cast<uint32_t>(regs_.dbg_cause >> 32);
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                RISCV_info("Get dbg_cause[63:32] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 8:
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                trans->rpayload.b32[i] = static_cast<uint32_t>(regs_.dbg_epc);
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                RISCV_info("Get dbg_epc[31:0] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 9:
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                trans->rpayload.b32[i] =
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                    static_cast<uint32_t>(regs_.dbg_epc >> 32);
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                RISCV_info("Get dbg_epc[63:32] = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 10:
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                trans->rpayload.b32[i] = regs_.irq_lock;
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                RISCV_info("Get irq_ena = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            case 11:
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                trans->rpayload.b32[i] = regs_.irq_cause_idx;
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                RISCV_info("Get irq_cause_idx = %08x",
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                            trans->rpayload.b32[i]);
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                break;
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            default:
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                trans->rpayload.b32[i] = ~0;
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            }
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        }
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    }
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}
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void IrqController::raiseLine(int idx) {
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    if (regs_.irq_lock) {
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        irq_wait_unlock |= (~regs_.irq_mask & (1 << idx));
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        return;
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    }
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    if ((regs_.irq_mask & (0x1 << idx)) == 0) {
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        regs_.irq_pending |= (0x1 << idx);
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        icpu_->raiseSignal(CPU_SIGNAL_EXT_IRQ);   // PLIC interrupt (external)
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        RISCV_info("Raise interrupt", NULL);
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    }
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}
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}  // namespace debugger
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